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HDL Digital Up-Converter (DUC)

This example illustrates how to generate HDL code for a Digital Up-Converter (DUC). A DUC is a digital circuit which converts a digital baseband signal to a passband signal. The input baseband signal is sampled at a relatively low sampling rate, typically the digital modulation symbol rate. The baseband signal is filtered and converted to a higher sampling rate before modulating a direct digitally synthesized (DDS) carrier frequency.

The input signals are passed through three filtering stages. Each stage first filters the signals with a lowpass interpolating filter and then performs a sampling rate change. The DUC in this example is a cascade of two FIR Interpolation Filters and one CIC Interpolation Filter. The first FIR Interpolation Filter is a pulse shaping FIR filter that increases the sampling rate by 2 and performs transmitter Nyquist pulse shaping. The second FIR Interpolation Filter is a compensation FIR filter that increases the sampling rate by 2 and compensates for the distortion of the following CIC filter. The CIC Interpolation Filter increases the sampling rate by 32.

The filters are implemented in fixed-point mode. The input/output word length and fraction length are specified. The internal settings of the first two filters are specified, while the internal settings of the CIC filter are calculated automatically to preserve full precision.

Create Pulse Shaping FIR Filter

Create a 32-tap FIR Interpolator with interpolation factor of 2. The wordlength and fraclength are set to 16, 15 for input, output and internal settings.

pfir = [0.0007    0.0021   -0.0002   -0.0025   -0.0027    0.0013    0.0049    0.0032 ...
       -0.0034   -0.0074   -0.0031    0.0060    0.0099    0.0029   -0.0089   -0.0129 ...
       -0.0032    0.0124    0.0177    0.0040   -0.0182   -0.0255   -0.0047    0.0287 ...
        0.0390    0.0049   -0.0509   -0.0699   -0.0046    0.1349    0.2776    0.3378 ...
        0.2776    0.1349   -0.0046   -0.0699   -0.0509    0.0049    0.0390    0.0287 ...
       -0.0047   -0.0255   -0.0182    0.0040    0.0177    0.0124   -0.0032   -0.0129 ...
       -0.0089    0.0029    0.0099    0.0060   -0.0031   -0.0074   -0.0034    0.0032 ...
        0.0049    0.0013   -0.0027   -0.0025   -0.0002    0.0021    0.0007 ];

hpfir = mfilt.firinterp(2, pfir);
set(hpfir, ...
    'arithmetic', 'fixed', ...
    'filterinternals', 'specifyprecision', ...
    'roundmode', 'nearest', ...
    'inputwordlength', 16, ...
    'inputfraclength', 15, ...
    'coeffwordlength', 16, ...
    'outputwordlength', 16, ...
    'outputfraclength', 15, ...
    'accumwordlength', 16, ...
    'accumfraclength', 15);

Create Compensation Fir Filter

Create an 11-tap FIR Interpolator with interpolation factor of 2. The wordlength and fraclength are set to 16, 15 for input, output and internal settings.

cfir = [-0.0007   -0.0009    0.0039    0.0120    0.0063   -0.0267   -0.0592   -0.0237 ...
         0.1147    0.2895    0.3701    0.2895    0.1147   -0.0237   -0.0592   -0.0267 ...
         0.0063    0.0120    0.0039   -0.0009   -0.0007];

hcfir = mfilt.firinterp(2, cfir);
set(hcfir, ...
    'arithmetic', 'fixed', ...
    'filterinternals', 'specifyprecision', ...
    'roundmode', 'nearest', ...
    'inputwordlength', 16, ...
    'inputfraclength', 15, ...
    'coeffwordlength', 16, ...
    'outputwordlength', 16, ...
    'outputfraclength', 15, ...
    'accumwordlength', 16, ...
    'accumfraclength', 15);

Create CIC Interpolating Filter

Create a 5-stage CIC Interpolator with interpolation factor of 32. The input wordlength and fraclength are set to 16, 15. The output wordlength is set to 20. The output fraclength and filter internals are calculated automatically to preserve full precision.

hcic = mfilt.cicinterp(32, 1, 5, 16, 20);
hcic.inputfraclength = 15;

Cascade of the Filters

Create a cascade filter including the above three filters. Check the frequency response of the cascade filter.

hduc = cascade(hpfir, hcfir, hcic);
fvtool(hduc);

Generate VHDL Code for DUC

Generate synthesizable and portable VHDL code for the cascade filter.

You have the option of generating a VHDL, Verilog, or ModelSim® .do file test bench to verify that the HDL design matches the MATLAB® filter.

To generate Verilog instead of VHDL, change the value of the property 'TargetLanguage', from 'VHDL' to 'Verilog'.

workingdir = tempname;
generatehdl(hduc,'Name', 'hdlduc', 'TargetLanguage', 'VHDL',...
            'TargetDirectory', workingdir);
### Starting VHDL code generation process for filter: hdlduc
### Cascade stage # 1
### Starting VHDL code generation process for filter: hdlduc_stage1
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage1.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage1.vhd</a>
### Starting generation of hdlduc_stage1 VHDL entity
### Starting generation of hdlduc_stage1 VHDL architecture
Warning: Using the SumFormat for a product stage in fir to be compatible with
MATLAB filter. 
### Successful completion of VHDL code generation process for filter: hdlduc_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: hdlduc_stage2
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage2.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage2.vhd</a>
### Starting generation of hdlduc_stage2 VHDL entity
### Starting generation of hdlduc_stage2 VHDL architecture
Warning: Using the SumFormat for a product stage in fir to be compatible with
MATLAB filter. 
### Successful completion of VHDL code generation process for filter: hdlduc_stage2
### Cascade stage # 3
### Starting VHDL code generation process for filter: hdlduc_stage3
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage3.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage3.vhd</a>
### Starting generation of hdlduc_stage3 VHDL entity
### Starting generation of hdlduc_stage3 VHDL architecture
### Section # 1 : Comb
### Section # 2 : Comb
### Section # 3 : Comb
### Section # 4 : Comb
### Section # 5 : Comb
### Section # 6 : Integrator
### Section # 7 : Integrator
### Section # 8 : Integrator
### Section # 9 : Integrator
### Section # 10 : Integrator
### Successful completion of VHDL code generation process for filter: hdlduc_stage3
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc.vhd</a>
### Starting generation of hdlduc VHDL entity
### Starting generation of hdlduc VHDL architecture
### Successful completion of VHDL code generation process for filter: hdlduc
### HDL latency is 225 samples

Generate VHDL Test Bench

Generate a stimulus signal for the filter. The length of the stimulus should be greater than the total latency of the filter.

Generate a VHDL test bench to verify that the results match the MATLAB results exactly. This is done by passing another property 'GenerateHDLTestbench' and setting its value to 'on'. The stimulus to test bench is specified using the 'TestBenchUserStimulus' property.

t = 0.005:0.005:1.5;
stim = chirp(t, 0, 1, 150);

generatehdl(hduc, 'Name', 'hdlduc',...
                 'TargetLanguage', 'VHDL',...
                 'TargetDirectory', workingdir, ...
                 'GenerateHDLTestbench', 'on', ...
                 'TestBenchUserStimulus', stim);
### Starting VHDL code generation process for filter: hdlduc
### Cascade stage # 1
### Starting VHDL code generation process for filter: hdlduc_stage1
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage1.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage1.vhd</a>
### Starting generation of hdlduc_stage1 VHDL entity
### Starting generation of hdlduc_stage1 VHDL architecture
Warning: Using the SumFormat for a product stage in fir to be compatible with
MATLAB filter. 
### Successful completion of VHDL code generation process for filter: hdlduc_stage1
### Cascade stage # 2
### Starting VHDL code generation process for filter: hdlduc_stage2
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage2.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage2.vhd</a>
### Starting generation of hdlduc_stage2 VHDL entity
### Starting generation of hdlduc_stage2 VHDL architecture
Warning: Using the SumFormat for a product stage in fir to be compatible with
MATLAB filter. 
### Successful completion of VHDL code generation process for filter: hdlduc_stage2
### Cascade stage # 3
### Starting VHDL code generation process for filter: hdlduc_stage3
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage3.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_stage3.vhd</a>
### Starting generation of hdlduc_stage3 VHDL entity
### Starting generation of hdlduc_stage3 VHDL architecture
### Section # 1 : Comb
### Section # 2 : Comb
### Section # 3 : Comb
### Section # 4 : Comb
### Section # 5 : Comb
### Section # 6 : Integrator
### Section # 7 : Integrator
### Section # 8 : Integrator
### Section # 9 : Integrator
### Section # 10 : Integrator
### Successful completion of VHDL code generation process for filter: hdlduc_stage3
### Generating: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc.vhd</a>
### Starting generation of hdlduc VHDL entity
### Starting generation of hdlduc VHDL architecture
### Successful completion of VHDL code generation process for filter: hdlduc
### HDL latency is 225 samples
### Starting generation of VHDL Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 300 samples.
Warning: The input stimulus length 300 is less than 4764, length of the impulse
response of the filter. Consider adding more input samples. 
### Generating Test bench: <a href="matlab:edit('/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_tb.vhd')">/tmp/BR2014bd_145981_71764/tpc48ef203_f813_407a_9ae4_3967d9fbbe72/hdlduc_tb.vhd</a>
### Creating stimulus vectors ...
### Done generating VHDL Test Bench.

ModelSim® Simulation Results

The following display shows the ModelSim HDL simulator running these test benches.

DUC response to the a chirp stimulus:

Conclusion

In this example, you designed three individual interpolation filters, cascaded them into a Digital-Up Converter, verified the frequency response of the filter, and called Filter Design HDL Coder™ functions to generate VHDL code for the filter and a VHDL test bench to verify the VHDL code against its MATLAB result. The simulation result of the VHDL code proved that the generated VHDL filter produced a bit-true implementation of the MATLAB filter.

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