HDL cosimulation with HDL Verifier lets you verify that your HDL code matches your MATLAB algorithm and Simulink models by providing visibility into the HDL code. You can assess how differences between expected results and HDL simulation could affect the design at the system level.
HDL Verifier provides an HDL Cosimulation Wizard that automatically connects Cadence® Incisive®, Mentor Graphics® ModelSim®, and Questa® HDL simulators to MATLAB and Simulink.
HDL Verifier exports your MATLAB algorithm or Simulink subsystem for use as a reference model in functional verification environments such as the Universal Verification Methodology (UVM). This approach can be used for real number modeling of digital, analog, and mixed-signal systems. By leveraging MATLAB Coder, Simulink Coder, or Embedded Coder, it generates a C model with a SystemVerilog Direct Programming Interface (DPI) for behavioral simulation in your EDA simulator. HDL Verifier also allows you to customize the generated SystemVerilog file, including the ability to tune parameters in the generated SystemVerilog module at simulation time.
The supported HDL Simulators include:
Generating DPI-C Models from MATLAB Using HDL Verifier
Generate a SystemVerilog DPI-C reference model for use in UVM simulation from MATLAB® using HDL Verifier™.
System Verilog DPI Component Generation (Example)
HDL Verifier automates the implementation of HDL code on FPGA boards to enable FPGA-in-the-loop (FIL) verification, which complements HDL cosimulation by enabling you to run test scenarios faster. As a result you can explore more test cases and perform extensive regression testing on your designs. This approach also ensures that the algorithm will behave as expected in the real world.
HDL Verifier supports FIL verification over the Gigabit Ethernet interface for Xilinx and Altera FPGA boards. See a list of supprted hardware in the documentation.
Using Custom Boards for FPGA-in-the-Loop Verification
Perform FPGA-based verification with custom boards using MATLAB® and Simulink® as test benches. Figures based on or adapted from figures and text owned by Xilinx, Inc. and used with permission. Copyright 2013 Xilinx, Inc.
When used with Simulink Coder™, HDL Verifier automatically generates IEEE® 1666 SystemC TLM 2.0 compatible transaction-level models. Generated SystemC models have a TLM 2.0 compliant interface with a target socket that uses the TLM 2.0 generic payload. You can select options for memory mapping, processing times, and input and output buffering. HDL Verifier also generates a SystemC test bench and a report that helps you navigate the generated code.
Transaction-Level Model Support (Example)
HDL Verifier works with HDL Coder™ to accelerate your FPGA and ASIC design and verification workflow. When you generate HDL code from HDL Coder, you can also generate an HDL cosimulation or FPGA-in-the-loop model.
HDL Verifier lets you integrate automatically generated code with your legacy HDL code using black-box integration. Together with HDL Coder, HDL Verifier completes the workflow for high-integrity applications that adhere to standards such as DO-254.
HDL Verifier supports HDL simulators including Cadence Incisive, Mentor Graphics ModelSim, and Synopsys® VCS. HDL Verifier also supports FPGA-in-the-loop verification over the Gigabit Ethernet interface for select Xilinx boards and over the Gigabit Ethernet or JTAG interface for select Altera FPGA boards.
To download the support package that enables FPGA-in-the-loop, view examples and videos, and obtain a list of boards supported, see:
For supported HDL simulators, see: