Stephan Van Beek, MathWorks
In this webinar learn how you can leverage our HDL Code Generation and Verification products to accelerate your ASIC and FPGA design cycle and avoid costly mistakes. Using Simulink HDL Coder you can prototype your algorithm on FPGAs or implement it on ASICs and FPGAs directly from Simulink. With EDA Simulator Link, you can co-simulate your HDL code with ModelSim and Cadence Incisive or perform FPGA based accelerated simulations.
MathWorks engineers demonstrate the latest enhancements to Simulink HDL Coder, which generates synthesizable Verilog® and VHDL® code from Simulink models, MATLAB code, and Stateflow charts.
Learn about the following topics:
Aufgezeichnet: 24 Aug 2011