Semiconductor Design & Verification North America Webinar Series – 2025 Part 2
Overview
Join our webinar series to learn how digital RTL (Register Transfer Level) design can be streamlined using MATLAB and Simulink. Through real-world examples and hands-on demonstrations, you’ll discover how to model, simulate, verify, and prepare your digital designs for hardware implementation using industry-standard workflows.
| Date | Topic | |
|---|---|---|
| 4 Sep 2025 |
From Model to Silicon: Mastering Resource-Efficient RTL generation 
Stephan van BeekMathWorksStephan brings over 17 years of experience at MathWorks, Eindhoven, as a technical specialist addressing the Systems Engineering and Embedded Systems (i.e., ASIC, FPGA and SoC) landscape. Stephan works with customers across Europe to apply the principles of Model-Based Systems Engineering with Model-Based Design. Prior to joining MathWorks, Stephan was a member of the electronic design methodology team at Océ-Nederland, where he focused on enhancing design workflows. His professional journey also includes a chapter at Anorad Europe BV, delving into the intricacies of motion control systems. Stephan earned his B.Sc. degree in Electrical Engineering from the Eindhoven University of Applied Sciences. |
Watch video (37:25) |
| 25 Sep 2025 |
From Model to Silicon: Proven Techniques to Verify Implementation of Algorithms in ICs 
Eric CiganMathWorksEric is responsible for product management and product marketing in the HDL and SoC design and verification product group. Prior to joining MathWorks in 2007, Eric held product management and business development roles with companies including Mentor Graphics, MathStar, and Analogy in the fields of digital and mixed-signal simulation, high-level synthesis, and hardware/software coverification. Eric earned S.B. and S.M. degrees in mechanical engineering from the Massachusetts Institute of Technology. |
Watch video (44:23) |
| 28 Oct 2025 |
From Model to Silicon: Efficient Digital Filter Design and Hardware Implementation 
Tom HenigeMathWorksTom supports customers in adopting MathWorks HDL code generation and verification products. He brings more than 20 years of experience in FPGA design and verification, with a background that includes next-generation wireless systems at Samsung Research America, aerospace communications and telemetry at Southwest Research Institute, and data acquisition systems at Texas Instruments. Tom holds a B.S. in Electrical Engineering from Texas A&M University and is an inventor on multiple patents in channel coding hardware design. |
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