Learn how to improve verification of ASIC and FPGA implementation of MATLAB algorithms and Simulink models through the combination of model verification and validation techniques with generation and verification of RTL code.
Functional verification of ASICs and FPGAs accounts for 50-70 percent of total design effort, and surveys show that achieving coverage closure is the single biggest challenge that design teams face before achieving signoff.
In this webinar, we will cover these topics to address verification challenges.
- Developing test cases to verify high-level functional behavior
- Evaluating model coverage metrics and expanding model coverage
- Generating verification components directly from the verified system-level models
- Generating RTL from MATLAB code and Simulink models
- Establishing traceability from requirements through models, RTL implementations and ASIC / FPGA verification environments.
MathWorks engineers will demonstrate use of these techniques on example designs verified using the Universal Verification Methodology (UVM).
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.