Verilog Test Bench and VHDL Test Bench

Verify FPGA and ASIC designs created in MATLAB and Simulink

A conventional Verilog® test bench, or a VHDL® test bench, is a code module that uses hardware description languages (HDL) to describe the stimulus to a logic design and check whether the design’s outputs match its specification. Many engineers use MATLAB® and Simulink® to create system test benches for specification models because the software provides productive and compact notation to describe algorithms, as well as visualization tools for examining algorithm behavior. They then develop Verilog and VHDL test benches based on the system test benches.

MATLAB or Simulink users have several options for verifying that HDL algorithm realizations are correct without manually coding Verilog or VHDL test benches.

Verification Using HDL Cosimulation

Instead of writing a Verilog or VHDL test bench, you can use a MATLAB or Simulink test bench in combination with an HDL simulator to verify your design under test (DUT). HDL Verifier™ automates this cosimulation process. The MATLAB or Simulink test bench compares output values from the HDL simulator with expected values from a truth model and reports "miscompares."

Verification Using FPGA-in-the-Loop Testing

You can also use a MATLAB or Simulink test bench with a DUT that has been programmed into a Xilinx®,  Intel® or Microsemi® FPGA development board through FPGA-in-the-loop simulation. You can use HDL Verifier with FPGA vendor tools to compile the HDL, build a programming file, load the file onto the development board, and enable communication between the MATLAB or Simulink session and the board. With FPGA-in-the-loop, there is no need to generate a Verilog test bench or VHDL test bench because MATLAB or Simulink serves this purpose.

Verification Using SystemVerilog DPI Test Bench

Another alternative to using a Verilog or VHDL test bench is based on exporting code to HDL simulators. SystemVerilog, an extension of Verilog used for test bench development, is supported by all popular HDL simulators. With the SystemVerilog Direct Programming Interface (DPI), you can integrate C/C++ code with simulators such as Synopsys® VCS®, Cadence Xcelium™, and Mentor Graphics® ModelSim® or Questa®. Using HDL Verifier in combination with MATLAB Coder™ or Simulink Coder™, you can generate SystemVerilog DPI test benches to verify products.

HDL Verifier can generate SystemVerilog DPI test benches in two different forms:

  • Component test bench: If you generate a C component from a Simulink subsystem for use as a DPI component, you can generate a SystemVerilog test bench. The test bench verifies the generated DPI component against data vectors from your Simulink model. (See Generate SystemVerilog DPI Component.)
  • HDL code test bench: If you generate HDL code from a Simulink subsystem using HDL Coder™, you can generate a SystemVerilog test bench. This test bench compares the output of the HDL implementation against the results of the Simulink model. (See Verify HDL Design Using SystemVerilog DPI Test Bench) If you generate HDL code from a Simulink subsystem using HDL Coder, you can optionally generate a SystemVerilog test bench. This test bench compares the output of the HDL implementation against the results of the Simulink model.

See also: MATLAB for FPGA, ASIC, and SoC development, HDL Coder, HDL Verifier, Vision HDL Toolbox, MATLAB Coder, Simulink Coder