Eric Cigan, MathWorks
In this video from the 2015 Altera SoC Developers Forum, a MathWorks engineer presents a hardware/software workflow targeting Intel SoC FPGAs using Model-Based Design.
Designing for this new class of devices -- SoC FPGAs -- presents a technical challenge because of the need to combine conventional workflows for embedded software and hardware design.
Using simulation to evaluate algorithms, automation to target algorithms to prototype hardware, and algorithmic C / HDL code generation as a path to production, design teams have been able to shorten product development times and improve quality using this workflow.
- Modeling algorithms and test benches for simulation and code generation, including hardware/software partitioning
- Generation of target-optimized C and building executables for the Cortex-A9 core
- IP core generation targeting the SoC programmable logic
- Extending a workflow using reference designs and customized hardware targeting
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