Convert 1-D to 2-D

Reshape 1-D or 2-D input to 2-D matrix with specified dimensions

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Libraries:
DSP System Toolbox / Signal Management / Signal Attributes
DSP System Toolbox HDL Support / Signal Management

Description

The Convert 1-D to 2-D block reshapes a length-M_i 1-D vector or an M_i-by-N_i matrix to an M_o-by-N_o matrix, where M_o is specified by the Number of output rows parameter and N_o is specified by the Number of output columns parameter.

y = reshape(u,Mo,No)					% Equivalent MATLAB code 

The input is reshaped column-wise, as shown in the two cases below. The length-6 vector and the 2-by-3 matrix are both reshaped to the same 3-by-2 output matrix.

An error is generated when (M_o*N_o)≠(M_i*N_i). In other words, the total number of input elements must be conserved in the output.

The output is frame based when you select the Frame-based output check box; otherwise, the output is sample based.

Ports

Input

Port_1 — Input signal

vector | matrix

Input signal, specified as a 1-D vector or 2-D matrix.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Output

Port_1 — Output signal

matrix

Output signal, returned as a 2-D matrix.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

Parameters

Number of output rows — Number of rows in output matrix

1 (default) | positive integer

Number of rows M_o in the output matrix, specified as a positive integer.

Number of output columns — Number of columns in output matrix

1 (default) | positive integer

Number of columns N_o in the output matrix, specified as a positive integer.

Frame-based output — Option to enable frame-based output

off (default) | on

Select this parameter to create a frame-based output.

Block Characteristics

Data Types	Boolean | double | fixed point | integer | single
Direct Feedthrough	no
Multidimensional Signals	no
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has a pass-through implementation.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Complex Data Support

This block supports code generation for complex signals.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a