Finite impulse response filter—optimized for HDL code generation
The dsp.HDLFIRFilter
System object™ models finite-impulse response filter architectures optimized for HDL code
generation. The object accepts one input sample at a time, and provides an option for
programmable coefficients. It provides a hardware-friendly interface with input and output
control signals. To provide a cycle-accurate simulation of the generated HDL code, the object
models architectural latency including pipeline registers and resource sharing.
The object provides three filter structures. The direct form systolic architecture provides a fully parallel implementation that makes efficient use of Intel® and Xilinx® DSP blocks. The direct form transposed architecture is a fully parallel implementation and is suitable for FPGA and ASIC applications. The partly-serial systolic architecture provides a configurable serial implementation that makes efficient use of FPGA DSP blocks. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.
All three structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters. The parallel implementations also remove the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms.
The latency between valid input data and the corresponding valid output data depends on the filter structure, serialization options, the number of coefficients and whether the coefficient values provide optimization opportunities.
For a FIR filter with multichannel or frame-based inputs, use the dsp.FIRFilter
System object instead of this System object.
To filter input data with an HDL-optimized FIR filter:
Create the dsp.HDLFIRFilter
object and set its properties.
Call the object with arguments, as if it were a function.
To learn more about how System objects work, see What Are System Objects?.
creates an
HDL-optimized discrete FIR filter System object, firFilt
= dsp.HDLFIRFilterfirFilt
, with default properties.
firFilt = dsp.HDLFIRFilter(num)
creates a filter with the
Numerator
property set to
num
.
sets
properties using one or more name-value pairs. Enclose each property name in single
quotes.firFilt
= dsp.HDLFIRFilter(___,Name,Value
)
For example:
Numerator = firpm(10,[0,0.1,0.5,1],[1,1,0,0]); fir = dsp.HDLFIRFilter(Numerator,'FilterStructure','Direct form transposed'); ... [dataOut,validOut] = fir(dataIn,validIn);
[
returns dataOut
,validOut
,ready
]
= firFilt(dataIn
,validIn
)ready
set to true
when the object is ready
to accept new input data on the next call.
The object returns the ready
argument only when you set the
FilterStructure
property to 'Partly serial
systolic'
. For example:
firFilt = dsp.HDLFIRFilter(Numerator,... 'FilterStructure','Partly serial systolic',... 'SerializationOption','Minimum number of cycles between valid input samples',... 'NumberOfCycles',8) ... for k=1:length(dataIn) [dataOut,validOut,ready] = firFilt(dataIn(k),validIn(k));
[
filters data using the coefficients, dataOut
,validOut
]
= firFilt(dataIn
,validIn
,coeff
)coeff
. The object expects the
coeff
argument only when you set the
NumeratorSource
property to 'Input port (Parallel
interface)'
. For example:
firFilt = dsp.HDLFIRFilter(NumeratorSource,'Input Port (Parallel interface)') ... for k=1:length(dataIn) Numerator = myGetNumerator(); %calculate coefficients [dataOut,validOut] = firFilt(dataIn(k),validIn(k),Numerator);
[
filters data when dataOut
,validOut
]
= firFilt(dataIn
,validIn
,reset
)reset
is false
. When
reset
is true
, the object resets the filter
registers. The object expects the reset
argument only when you set
the ResetInputPort
property to true
. For example:
firFilt = dsp.HDLFIRFilter(Numerator,'ResetInputPort',true) ... % reset the filter firFilt(0,false,true); for k=1:length(dataIn) [dataOut,validOut] = firFilt(dataIn(k),validIn(k),false);
To use an object function, specify the
System object as the first input argument. For
example, to release system resources of a System object named obj
, use
this syntax:
release(obj)
Reset Behavior
By default, the dsp.HDLFIRFilter
object connects the generated
HDL global reset to only the control path registers. The two reset properties,
ResetInputPort and HDLGlobalReset, connect a reset signal to the data path registers.
Because of the additional routing and loading on the reset signal, resetting data
path registers can reduce synthesis performance .
The ResetInputPort
property enables the
reset
argument of the object. The reset signal implements a
local synchronous reset of the data path registers. For optimal use of FPGA
resources, this option does not connect the reset signal to registers targeted to
the DSP blocks of the FPGA.
The HDLGlobalReset
property connects the generated HDL global
reset signal to the data path registers. This property does not change the arguments
of the object or modify simulation behavior in MATLAB. The generated HDL global reset can be synchronous or asynchronous
depending on your HDL code generation settings. Depending on your device, using the
global reset might move registers out of the DSP blocks and increase resource
use.
When you set both the ResetInputPort
and
HDLGlobalReset
properties to true
, the
global and local reset signals clear the control and data path registers.
This System object implements the algorithms described on the Discrete FIR Filter HDL Optimized block reference page.