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Computes fast fourier transform (FFT) and generates optimized HDL code

**Library:**DSP System Toolbox HDL Support / Transforms

The FFT HDL Optimized block provides two architectures that implement the algorithm for FPGA and ASIC applications. You can select an architecture that optimizes for either throughput or area.

`Streaming Radix 2^2`

— Use this architecture for high-throughput applications. This architecture supports scalar or vector input data. You can achieve giga sample per second (GSPS) throughput using vector input.`Burst Radix 2`

— Use this architecture for a minimum resource implementation, especially with large fast fourier transform (FFT) sizes. Your system must be able to tolerate bursty data and higher latency. This architecture supports only scalar input data.

The FFT HDL Optimized block replaces the HDL Streaming FFT block and the HDL Minimum Resource FFT block. The FFT HDL Optimized block accepts real or complex data, provides hardware-friendly control signals, and optional output frame control signals.

[1] Algnabi, Y.S, F.A. Aldaamee, R.
Teymourzadeh, M. Othman, and M.S. Islam. “Novel architecture of pipeline Radix 2^2 SDF
FFT Based on digit-slicing technique.” *10th IEEE International Conference on
Semiconductor Electronics (ICSE)*. 2012, pp. 470–474.