Hardware-Software Co-Design Basics
You can use the hardware-software co-design workflow to partition your design to run on
SoC platforms. With the HDL Workflow Advisor, you can use the
Generation workflow to generate an HDL IP core that runs on the FPGA on board the
SoC. Using Embedded Coder®, you can generate and build the embedded software, and run it on the
- Hardware-Software Co-Design Workflow for SoC Platforms
High-level workflow steps for targeting an SoC platform.
- Getting Started with the HDL Workflow Advisor
Learn the basics of the HDL Workflow Advisor and how to run various tasks.
- Run HDL Workflow with a Script
Export, import, or configure an HDL Workflow CLI command script.
- Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
- Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
- Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.