When you partition your design into hardware and software components, use the HDL Coder™ HDL Workflow Advisor to target your design on standalone FPGA boards, SoC devices, and Speedgoat FPGA IO modules. The design consists of the DUT algorithm for which you generate the RTL code and IP core. You can integrate the IP core into a reference design for the target platform. To test the HDL IP core functionality, you can use a generated software interface model or a software interface script.
|Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface|
|Write data to IP core or read data from IP core using AXI4-Stream interface|
|Maps a DUT port to specified AXI4 interface in HDL IP core|
|Write data to a DUT port from MATLAB|
|Reads output data and returns it with the port data type and dimension|
|Release the hardware resources associated with the fpga object|
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
How to design your model for AXI4-Stream vector or scalar interface generation.
How to design your model for IP core generation with AXI4-stream video interfaces.
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
Generate software interface script to communicate with the HDL IP core and perform rapid prototyping.
Generate software interface model to communicate with the HDL IP core and perform rapid prototyping.
Create and author a software interface script by configuring interfaces and port mapping information to control HDL IP core.