Multicycle Path Constraints Parameters
This page describes configuration parameters that reside in the HDL Code Generation > Optimization > General tab of the Configuration Parameters dialog box. Synthesis tools require that data propagates from a source register to a destination register within one clock cycle. Multicycle paths cannot complete their execution within one clock cycle and cannot meet the timing requirements. To meet the timing requirement of multicycle paths, use the multicycle path constraints parameters to generate a register-to-register path information file or to generate enable-based constraints that use the timing controller enable signals.
To meet the timing requirement of the multicycle path in your model, use enable-based
constraints. The constraints are applied to a model that has Clock
inputs set to
Single. This option is useful for a
multirate model to create a constraint file for relaxing timing of the slow-rate regions.
Enable-based constraints relax the timing requirement by enabling multiple clock cycles for data to propagate between the registers. The constraints use the timing controller enable signals to create enable-based register groups that have registers in each group driven by the same clock enable.
When you enable this setting and generate HDL code, HDL Coder™ generates a constraints file with the naming convention
dutname_constraints. The format of the file name depends on the synthesis tool that you specify. The constraints file defines the timing requirements of multicycle paths. The file contains information about the clock multiples for calculating the setup and hold time information.
Do not generate a multicycle path constraints file.
When you select the Enable-based constraints check box, make sure that Clock-rate pipelining is
Off. Using enable-based multicycle path constraints is an alternative to the clock-rate pipelining optimization. You can clear the clock-rate pipelining check box in the HDL Code Generation > Optimization > Pipelining tab.
Set the Clock inputs to
Single. You can set the clock input in the HDL Code Generation > Global settings > Clock settings > Clock inputs.
To generate multicycle path constraints file, oversampling factor must be greater than 1. You can specify the oversampling value in the HDL Code Generation > Global settings > Clock settings > Oversampling factor.
|Type: character vector|
For example, you can enable the
when you generate HDL code for the
symmetric_fir subsystem inside the
sfir_fixed model by using either of these methods:
Pass the property as an argument to the
makehdl('<model_name>', ... 'MulticyclePathConstraints','on')
When you use
hdlset_param, set the parameter on the model, and then generate HDL code by using