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Naming and Layout Options for Model Generation

Following are the different naming options available in HDL Code Generation > Global Settings pane under the Model Generation tab. You can control the prefix for the generated model name and the suffix for the validation model name.

Prefix for generated model name

Specify the prefix of the generated model name.

Settings

Default: 'gm_'

Specify the prefix as a character vector. HDL Coder™ appends the prefix to name of generated model.

Command-Line Information

Property: GeneratedModelNamePrefix
Type: character vector
Default: 'gm_'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to indicate that you are using the generated model as a software interface model, you can use the prefix sm_. Specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
            'GeneratedModelNamePrefix','sm_')
  • When you use hdlset_param, set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','GeneratedModelNamePrefix','sm_')
    makehdl('sfir_fixed/symmetric_fir')

Dependency

To specify Prefix for generated model, select Generated model.

See Also

Suffix for validation model name

Specify the suffix of the validation model name.

Settings

Default:'_vnl'

Specify the suffix as a character vector. HDL Coder appends the suffix to name of validation model.

Command-Line Information

Property: ValidationModelNameSuffix
Type: character vector
Default: '_vnl'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to indicate that you are using the generated model as a software interface model, you can use the suffix _sm for the validation model name. Specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','ValidationModelNameSuffix','_sm')
  • When you use hdlset_param, set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','ValidationModelNameSuffix','_sm');
    makehdl('sfir_fixed/symmetric_fir');

Dependency

To specify Suffix for validation model, select Generated model and Validation model.

See Also

Layout Style

Select the layout style of the generated HDL model for better layout visualization.

Layout StyleDescription
None

When you set the Layout style to None, the generated model has no layout. Use this layout style when you want to test only functionality. The code generation time is significantly reduced.

Default

When you set the Layout style to Default, the model is generated using default HDL coder layout. Use this layout style when you want to verify the configured optimizations on the input model by using optimization reports.

You can set the Auto signal routing to on or off based on the layout visualization and code generation time.

When the design complexity is high, the layout process might not succeed. Code generation does not proceed after the '### Begin model generation' message in the command log. In such a scenario, you can switch layout option to None or change the style to AutoArrange.

AutoArrange

When you set the Layout style to AutoArrange, the model is generated by using a Simulink® layout. Use this layout style when you want to verify the configured optimizations on the input model by using optimization reports.

Note

For an input model that has no optimizations configured, you cannot observe the layout effect of these layout styles. The generated model appears the same as the input model.

Settings

Default: Default

Command-Line Information

Property: LayoutStyle
Type: character vector
Value: 'None' | 'Default'| 'AutoArrange'
Default: 'Default'

To set this property, use hdlset_param,

hdlset_param(gcs,'LayoutStyle','Default')

Tips

  • Consider introducing hierarchy in the model to reduce the complexity and number of blocks to be placed in a single level. Such model refactoring helps improve the layout computation process.

  • The code generation time increases when you change the layout style to Default or AutoArrange.

Dependency

To select Layout style, first select Generated model.

See Also

Model Generation Parameters for HDL Code

Auto signal routing

Specify automatic routing of signals in the generated model.

Settings

Default: on

Command-Line Information

Property: autoroute
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use hdlset_param:

hdlset_param(gcs,'autoroute','on')

Dependency

To select Auto signal routing, first select Layout style to Default.

See Also

Model Generation Parameters for HDL Code

Inter-block horizontal scaling

Scale the generated model horizontally. You can use this setting for Inter-block vertical scaling depending on how tightly or loosely packed you want the model to appear.

Settings

Default: 1.7

Command-Line Information

Property: InterBlkHorzScale
Type: positive integer | positive double
Default: 1.7

To set this property, use hdlset_param:

hdlset_param(gcs,'InterBlkHorzScale', 1.7)

Dependency

To select Inter-block horizontal scaling, set Layout style to Default.

See Also

Model Generation Parameters for HDL Code

Inter-block vertical scaling

Scale the generated model vertically. You can use this setting for Inter-block horizontal scaling depending on how tightly or loosely packed you want the model to appear.

Settings

Default: 1.2

Command-Line Information

Property: InterBlkVertScale
Type: positive integer | positive double
Default: 1.2

To set this property, use hdlset_param:

hdlset_param(gcs,'InterBlkVertScale', 1.2)

Dependency

To select Inter-block horizontal scaling, set Layout style to Default.

See Also

Model Generation Parameters for HDL Code