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Model Configuration Parameters: Optimization

The Optimization category enables you to specify various optimizations such as delay balancing, resource sharing and pipelining. To improve the area and timing of your design on the target hardware, specify these settings.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > General category.

ParameterDescription
Map pipeline delays to RAMMap pipeline registers in the generated HDL code to RAM.
RAM mapping thresholdSpecify the minimum RAM size for mapping to block RAMs.
Transform non zero initial value delaySpecify Transform Delay blocks to have zero initial value.
Remove Unused PortsRemove unused ports from the design.
Enable-based constraintsMeet the timing requirement of the multicycle path in your model.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Pipelining category.

ParameterDescription
Allow design delay distributionWhether to allow distributed pipelining and delay absorption optimizations to move design delays.
Pipeline distribution priorityPriority for the distributed pipelining and delay absorption optimizations.
Clock-rate pipeliningInsert pipeline registers at a clock rate that is faster than the data rate.
Allow clock-rate pipelining of DUT output portsProduce the DUT outputs as soon as possible by passing the outputs from the DUT at the clock rate rather than the data rate.
Balance clock-rate pipelined DUT output portsSynchronize the DUT outputs while satisfying the highest-latency requirements of the outputs.
Distributed pipeliningEnable pipeline register distribution.
Use synthesis estimates for distributed pipeliningDetermine more accurate propagation delays for each component.
Adaptive pipeliningInsert pipeline registers to the blocks in your design, reduce the area usage, and maximize the achievable clock frequency on the target FPGA device.
Map lookup tables to RAMLookup tables in your design to block RAM and reduce area usage on the target FPGA device.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Resource Sharing category.

ParameterDescription
Share AddersShare adders with the resource sharing optimization.
Adder sharing minimum bitwidthSpecify the minimum bit width that is required to share adders with the resource sharing optimization.
Share MultipliersShare multipliers with the resource sharing optimization.
Multiplier sharing minimum bitwidthSpecify the minimum bit width that is required to share multipliers with the resource sharing optimization.
Multiplier promotion thresholdShare smaller multipliers with other larger multipliers by using the resource sharing optimization.
Multiplier partitioning thresholdPartition multipliers based on a threshold.
Multiply-Add blocksShare Multiply-Add blocks with the resource sharing optimization.
Multiply-Add block sharing minimum bitwidthSpecify the minimum bit width that is required to share Multiply-Add with the resource sharing optimization.
Atomic subsystemsShare Atomic Subsystem blocks with the resource sharing optimization.
MATLAB Function blocksShare MATLAB Function blocks with the resource sharing optimization.
Floating-Point IPsShare floating-point IPs in the design.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Optimization > Frame to Sample Conversion category.

ParameterDescription
Enable frame to sample conversionEnable frame-to-sample conversion.
Samples per cycleSpecify the size of the signals after the frame-to-sample conversion streams them.
Input FIFO sizeSpecify the register size of the generated input FIFOs around the streaming matrix partitions.
Output FIFO sizeSpecify the register size of the generated output FIFOs around the streaming matrix partitions.
Input processing orderChoose between row-major and column-major ordering for the frame inputs.
Delay size threshold for external memory (bits)Specify a threshold size in kilobytes to map large integer delays to input and output DUT ports and offload large delays to external memory outside of your FPGA.

The Configuration Parameters dialog box also includes other code generation parameters: