Functional Requirements Testing

Generate test cases for functional design requirements

Blocks

Blocks used in Test Case Generation

Test Condition	Constrain signal values in test cases
Test Objective	Define custom objectives that signals must satisfy in test cases
Detector	Detect true duration on input and construct output true duration based on output type
Extender	Extend true duration of input
Implies	Specify condition that produces a certain response
Within Implies	Verify response occurs within desired duration
Verification Subsystem	Specify proof or test objectives without impacting simulation results or generated code

Functions

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Functions used in Test Case Generation

`sldvoptions`	Create design verification options object
`sldv.condition`	Test condition function for Stateflow charts and MATLAB Function blocks
`sldv.test`	Test objective function for Stateflow charts and MATLAB Function blocks
`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvtimer`	Identify, change, and display timer optimizations
`sldvoptions`	Create design verification options object
`sldvrun`	Analyze model
`sldvlogsignals`	Log simulation input port values
`sldvgencov`	Analyze models to obtain missing model coverage
`sldvruntest`	Simulate model by using input data
`sldvruntestopts`	Generate simulation or execution options for `sldvruntest` or `sldvruncgvtest`
`sldvharnessopts`	Default options for `sldvmakeharness`
`sldvmakeharness`	Generate harness model
`sldvmergeharness`	Merge test cases and initializations into one harness model
`sldvreport`	Generate Simulink Design Verifier report
`sldvchecksum`	Returns checksum of model

Topics

Introduction to Test Case Generation

What Is Test Case Generation?

Brief overview of test case generation with Simulink^® Design Verifier™.

Workflow for Test Case Generation

Outlines a process for generating test cases for your model.

Use Test Generation Advisor to Identify Analyzable Components

Use the Test Generation Advisor to guide model and component analysis.

Configuring S-Function for Test Case Generation

This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.

Generate Test Cases for Embedded Coder Generated Code

Outlines a process for generating test cases for generated code.

Code Coverage Test Generation

This example shows how to use Simulink® Design Verifier™ to generate test cases to obtain complete code coverage.

Export Test Cases to Simulink Test

Describes how to generate test cases in Simulink Test™ using Simulink Design Verifier analysis results, which can be generated by property proving, design error detection, and test case generation.

What is a Specification Model?

Overview of specification model and its use in requirements-based verification.

Component Verification

What Is Component Verification?

An overview of the two approaches to component verification.

Functions for Component Verification

Describes the Simulink Design Verifier functions you can use for component verification.

Verify a Component for Code Generation

This example uses the slvnvdemo_powerwindow model to show how to verify a component in the context of the model that contains that component.

Isolate Verification Logic with Observers

Describes the observer support for simulink design verifier.

Parameter Constraint

Parameter Constraint Values

Overview of parameter configuration for Simulink Design Verifier analysis.

Define Constraint Values for Parameters

An example of how to specify parameters as variables for analysis.

Specify Parameter Constraint Values for Full Coverage

An example of how to specify parameter constraint values to achieve full model coverage.

Specify Constraint Values for Structure or Bus Parameters

This example describes how to generate tests that constrain the values for the structures and bus signals in a model.

Simulink Design Verifier Pane

Design Verifier Pane: Test Generation

Specify options that control how Simulink Design Verifier generates tests for the models it analyzes.

Design Verifier Pane: Parameters

Specify options that control how Simulink Design Verifier uses parameter configurations when analyzing models.

Design Verifier Pane

Specify analysis options and configure Simulink Design Verifier output.

Simulink Design Verifier Options

Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.

Review Analysis Results

Review analysis results in the Simulink Design Verifier Results Summary window.

Featured Examples

Test Condition Block

Constrain input values. The Test Condition block forces the input value to be either 0 or 1.

Open Example

Test Objective Block

The use of two custom Test Objective blocks. The block "True" forces the output signal to be 2. The block "Edge" inside "Masked Objective" specifies that the output signal transition from 2 to 1.

Open Example

Use a Specification Model for Requirements-Based Testing

Use a specification model to perform requirements-based testing. In this example, you follow a systematic approach to verify your design model against requirements. For a detailed description of specification model, see What is a Specification Model?.

Open Script