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Parameter Constraint Values

Parameter Configuration for Analysis

Simulink® Design Verifier™ software can treat parameters in your model as variables during its analysis. For example, suppose you specify a variable that is defined in the MATLAB® workspace as the value of a block parameter in your model. You can instruct Simulink Design Verifier to use additional values for that parameter in its analysis.

This allows you to, for example:

  • Extend the results of design error detection or property proving analysis to consider the impact of additional parameter values.

  • Generate comprehensive test cases for situations in which parameter values must vary to achieve more complete coverage results. For more information, see Specify Parameter Constraint Values for Full Coverage.

If you place a constraint on a parameter in your model, during analysis that parameter takes only your specified constraint value or values. A group of constraints on parameters in the same model is also called a parameter configuration.

Use the Parameter Table to manage constraints on your model parameters for analysis. In the Parameter Table, you can:

Data Types in Parameter Configurations

Consider the following issues related to data types when constraining parameter values:

Parameters Converted to Fixed Point in the Model

If your model references a base workspace parameter whose data type is auto, single, or double, and the model converts that parameter to a fixed-point data type, you must define the constraints for that parameter according to its fixed-point type.

Parameters Defined as Simulink.Parameter and Referenced by Multiple Locations

For a parameter defined as Simulink.Parameter or an inherited class of Simulink.Parameter whose data type is auto, if the parameter is referenced by multiple locations with different data types, Simulink Design Verifier cannot generate values for that parameter during the analysis.

Complex Data as Parameters not Supported

If the data type of a parameter in the MATLAB workspace is complex, Simulink Design Verifier does not support generating values for that parameter during the analysis.

Tuning Array of Structure or Bus Data types are not supported

Simulink Design Verifier does not support tuning array of structure or bus data types during the analysis.

Parameters in Variant Subsystems

Parameters can be used to select variants in Variant Subsystem blocks. These parameters are listed in the Parameter Table. However, Simulink Design Verifier only supports analyzing the active variant.

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