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release

Release JTAG cable resource

Description

example

release(mem) releases the JTAG cable resource, freeing the cable for use to reprogram the FPGA. After initialization, the AXI master object, mem, holds the JTAG cable resource, and other programs cannot access that JTAG cable. When you have an active AXI master object, FPGA programming over JTAG fails. Call the release object function before reprogramming the FPGA.

Examples

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For this example, you must have a design running on a hardware board connected to the MATLAB® host machine.

Create a MATLAB AXI master object. The object connects with the hardware board and confirms that the IP is present. You can create the object with a vendor name or an socHardwareBoard object.

mem = socAXIMaster('Xilinx');

Write and read one or more addresses with one command. By default, the functions auto-increment the address for each word of data. For instance, write ten addresses, then read the data back from a single location.

writememory(mem,140,[10:19])
rd_d = readmemory(mem,140,1)
rd_d =

  uint32

   10

Now, read the written data from ten locations.

rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   10   11   12   13   14   15   16   17   18   19

Set the BurstType property to 'Fixed' to turn off the auto-increment and access the same address multiple times. For instance, read the written data ten times from the same address.

rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d =

  1×10 uint32 row vector

   10   10   10   10   10   10   10   10   10   10

Write incrementing data ten times to the same address. The final value stored in address 140 is 29.

writememory(mem,140,[20:29],'BurstType','Fixed')
rd_d = readmemory(mem,140,10)
rd_d =

  1×10 uint32 row vector

   29   11   12   13   14   15   16   17   18   19

Alternatively, specify the address as a hexadecimal string. To cast the read data to a data type other than uint32, use the OutputDataType property.

writememory(mem,'1c',[0:4:64])
rd_d = readmemory(mem,'1c',16,'OutputDataType',numerictype(0,6,4))
rd_d = 

  Columns 1 through 10
         0    0.2500    0.5000    0.7500    1.0000    1.2500    1.5000    1.7500    2.0000    2.2500
  Columns 11 through 16
    2.5000    2.7500    3.0000    3.2500    3.5000    3.7500

          DataTypeMode: Fixed-point: binary point scaling
            Signedness: Unsigned
            WordLength: 6
        FractionLength: 4

When you are done accessing the board, release the JTAG connection.

release(mem)

Input Arguments

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JTAG connection to AXI master IP running on your hardware board, specified as an socAXIMaster object.

Introduced in R2019a