Create object to represent IP core running on FPGA board
socIPCore object represents an active IP core on an FPGA
board and provides read and write access to the IP.
myCoreObj = socIPCore(
socIPCore object that connects to an IP core running on an
FPGA board. The object uses an
to access memory locations in the IP core.
IPCoreInfo is a structure
generated when you run the SoC Builder tool and includes the board and IP
core configuration parameters from your model.
You can create
socIPCore objects representing any of these IPs:
Direct memory access (DMA)
Video DMA (VDMA)
Video timing controller (VTC)
High definition multimedia interface (HDMI)
myCoreObj = socIPCore(
sets properties using one or more name-value pairs. For
socIPCoreobject that connects to an IP core on the specified board and sets the performance monitor mode to profile mode.
axiMaster — Name of
socAXIMaster object used for memory-mapped
socAXIMaster object used for memory-mapped access,
specified as an
socAXIMaster object using the
function, and use the created object as an input to
mySocAXIObj = socAXIMaster('Xilinx'); myIPObj =
IPCoreInfo — IP core information
IP core information, specified as a structure generated by the SoC Builder
tool. To access the structure, load the
.mat file which is
generated by SoC Builder tool. The file is named
Loading the file will load the structures generated by the SoC Builder
tool to your workspace.
The structures contain information for vendor IP and for user-specified IP which are specific to your model and board. The structures are named as follows:
structrepresenting a frame buffer.
structrepresenting a performance monitor.
structrepresenting a video timing controller.
structrepresenting a VDMA-based HDMI IP.
structrepresenting an AXI traffic generator.
structrepresenting a user IP named "DUT".
mat file loads additional
structs for IPs,
for internal access.
IPCoreName — IP core object type
IP core object type, specified as one of the values in this table:
SoC Blockset™ memory traffic generator
|SoC Blockset performance monitor|
|Xilinx® VDMA IP|
|Analog Devices® DMA controller IP|
|Video timing controller|
|An IP used to trigger reading frames from the source (mm2s) VDMA|
|VDMA-based frame buffer IP|
|VDMA-based HDMI IP|
PerfMonMode — Type of performance data to collect
'Profile' (default) |
Type of performance data to collect, specified as
'Profile' mode to collect byte
and burst counts for bandwidth and latency plots.
'Trace' mode to
collect burst transaction event data for display as waveforms.
|Initialize IP core corresponding to |
|Start IP core execution on hardware board|
Introduced in R2019a