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Stream Audio Signal from Intel FPGA Board Using ready-to-capture Signal

This example shows you how to use ready to capture signal in a FPGA Data Capture with existing HDL code to read FPGA streaming signals. This example starts with an existing FPGA design that implements on-chip Analog to Digital Converter (ADC) to sample audio signal. The ADC IP exposes an Avalon Memory Mapped (MM) slave interface for control, and an Avalon streaming interface for data output. The existing example contains a simple Avalon MM master to start ADC. Use FPGA Data Capture to collect the ADC output data from the Avalon streaming interface, and stream it to the MATLAB workspace.

"ready_to_capture" is an output port of FPGA Data Capture HDL IP, that helps capture continuous data provided that user places a FIFO in front of the FPGA Data Capture HDL IP, and check the ready_to_capture signal before streaming data to the Data Capture IP. You might also need to check that the FIFO is not empty.

The audio data from Avalon streaming interface is written into a FIFO, and the FIFO is read when ready_to_capture signal is asserted. The FIFO should be large enough to capture data when ready_to_capture is deasserted to avoid data overflow. In this example, the FIFO depth is configured to 16K, and the audio sampling frequency is 50KHz.

Requirements and Prerequisites


  • HDL Verifier

  • HDL Verifier Support Package for Intel FPGA Boards

  • Fixed-Point Designer

  • Intel® Quartus Prime Software

  • Arrow® DECA MAX 10 FPGA Evaluation kit

  • DSP System Toolbox

Set Up FPGA Development Board

1. Make sure that the power switch remains OFF.

2. Connect the JTAG download cable between the FPGA development board and the host computer.

3. (Optional) Connect the line-in port of the FPGA board with an audio source, such as your cellphone, via 3.5 mm audio cable. If you skip this step, the captured data will be random noises.

Prepare Example Resources

Set up a working folder and provide MATLAB with access to your FPGA design software.

1. Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.

2. Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:

     cd C:\MyTests

3. To copy the example FPGA design files into your working directory, enter this MATLAB command:


4. Set up Intel Quartus. Here, we assume that the Intel Quartus executable is located in C:\altera\18.0\quartus\bin\quartus.exe. If the location of your executable is different, use your path instead.

     hdlsetuptoolpath('ToolName','Altera Quartus II','ToolPath','C:\altera\18.0\quartus\bin\quartus.exe');

Generate FPGA Data Capture Components

At the MATLAB command prompt, enter:


This command launches a graphical user interface (GUI). This example monitors one signal from the existing HDL code for the audio system. The signal is a 12-bit "adc_out". The "adc_out" is the digital samples of the audio line-in signal. To configure the data capture components to operate on this signal, make the following changes:

1. Name the signal to "adc_out" in the Ports table.

2. Change the bit width of the signal to 12.

3. Make sure the FPGA vendor is set to Altera.

4. Ensure the selected language is Verilog.

5. Keep the Sample depth at 8192. This is the number of samples of each signal that the data capture tool returns to MATLAB each time a trigger is detected.

The GUI now looks like this:

Finally, click the "Generate" button to generate FPGA Data Capture component. You should see a report that confirms the generation was successful.

Integrate the FPGA Data Capture HDL IP

You must include the generated HDL IP core into the example FPGA design. You can copy the module instance code from the generated report. In this example, we are going to connect the generated HDL IP with the ADC output via a FIFO.

Open the top.v file provided with this example. Add the following code immediately above the last line (endmodule) of that file.

  datacapture u0 (

We also placed above code in top.v file but commented it out. You can also uncomment that piece of code instead of adding it.

Save top.v, compile the modified FPGA design, and create an FPGA programming file by using the following tcl script.

     system('quartus_sh -t adc_deca_max10.tcl &')

The tcl scripts included in this example perform these steps:

1. Create a new Quartus project.

2. Add example HDL files and the generated FPGA Data Capture HDL files to the project.

3. Compile the design.

4. Program the FPGA.

Wait until the Quartus process successfully finishes before going to the next step. This process takes approximately 5 to 10 minutes.

Capture Data

First, go into the directory where the FPGA Data Capture component is generated.

     cd hdlsrc

User must set the capture mode to Immediate for ready to capture.

1. Instantiate FPGA Data Capture System object and Configure the trigger settings as follows:

  DataCaptureObj = datacapture;
  DataCaptureObj.TriggerPosition = 0;
  DataCaptureObj.NumCaptureWindows = 1;

2. Capture FPGA data continuously. In this example, we capture NumberOfSampledepth snapshots of data. You can modify the NumberOfSampledepth as needed.

  NumberOfSampledepth = 10;
  Sample_depth = 8192;
  adc_out =  int16(zeros(NumberOfSampledepth*Sample_depth, 1));
  for i=1: NumberOfSampledepth
    adc_out( i*Sample_depth-(Sample_depth-1) :i*Sample_depth) = step(DataCaptureObj);

3. Here the captured audio can saved by writing the captured data to .wav format, and process it or replay it at a later time.


4. View the captured data in Logic analyzer. The Logic Anlayzer may take few seconds to load the captured sanpshots of data.

  scope = dsp.LogicAnalyzer('NumInputPorts',1, 'DisplayChannelFormat', 'Analog', 'DisplayChannelHeight', 100);
  tags = getDisplayChannelTags(scope);
  modifyDisplayChannel(scope, tags{1}, 'Name', 'adc_out');

The following image shows 8K samples of audio data in the Logic Analyzer: