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setTriggerTimeOut

Configure maximum number of FDC IP core clock cycles within which trigger condition must occur in a trigger stage

Description

setTriggerTimeOut(DC,enable,value,N) configures the maximum number of FPGA Data Capture (FDC) IP core clock cycles, within which the trigger condition must occur in a trigger stage specified by N. DC is a customized data capture object. Use enable argument to enable the trigger time out in trigger stage N, specify the number of FDC IP core clock cycles using value argument.

Input Arguments

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Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

Indication that the trigger time out is part of the trigger stage, specified as a numeric or logical 1 (true) or 0 (false). To use the trigger time out in a particular trigger stage, set this value to 1 (true). When you set this value to 0 (false), the trigger time out is not used for the specified trigger stage.

Specify an integer from 1 to 65,536. Within this many FDC IP core clock cycles, the trigger condition must occur in a trigger stage specified by N.

Trigger stage, specified as an integer from 2 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool. Use N to set the trigger time out in Nth trigger stage. Trigger time out is not allowed for trigger stage 1.

Introduced in R2020b