Connect hardware logic to AD9361-based Zynq receiver
SoC Blockset Support Package for Xilinx Devices / SDR / AD9361
The AD9361 Rx block connects your hardware logic to the AD9361 receiver hardware. In simulation, this block returns data from a file or input port. This block does not connect to the radio hardware from simulation.
rxDataIn — Receiver data
Receiver data to pass through the block in simulation.
To enable this port, set the Simulation output parameter to
From input port.
rxDataOut — Receiver data
Receiver data, returned as a scalar. The Simulation output parameter defines the source of this data.
Simulation output — Simulation behavior
Zeros (default) |
From recorded file |
From input port
Simulation behavior, specified as one of these values:
Zeros–– Return zero-valued data.
From recorded file–– Return data from a file, using the Dataset name and Source name parameters.
From input port–– Pass through data from the input port.
Dataset name — Name of recorded file
rf_data_adsb.tgz (default) | file path
Name of recorded file, specified as a file path on the host PC or browse and select the file on the host PC. This block supports only TGZ files created using the SoC Blockset™ data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.
Source name — Name of dataset
RF data Ch-1 (default) | character vector
Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.
Sample time — Sample time of the block
1 (default) | positive scalar
Sample time of the block, specified as a positive scalar.
HDL Code Generation
Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.
To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.
Introduced in R2019a