AXI4-Register IIO Write (HOST)
Write data to memory-mapped registers from a simulation model
SoC Blockset Support Package for Xilinx Devices / Host I/O
The AXI4-Register IIO Write (HOST) block writes data to memory-mapped registers in the programmable logic of the connected Xilinx® SoC device from a running Simulink® model on the host computer. This block enables low-latency high-throughput data transmission between your simulation model and the FPGA registers on the SoC device.
The AXI4-Stream IIO Write (HOST) block sends data on the host computer to the register in the IP core on the SoC device. This block uses the Industrial I/O (IIO) library driver to create a network server daemon on the SoC device and host computer to pass the data between the host computer running the simulated portion of the model. This diagram shows the connection between the HDL Coder™ generated IP core, memory-mapped register, and communication bridge to the running Simulink model.
data — Data frame to DMA buffer
This port accepts an N-by-1 vector written to memory in the DMA buffer transfer.
Device name — File name of IP core device
Enter the name and channel of the IP core device on the FPGA as a colon-separated
list. If you are using HDL Coder to generate the IP core, HDL Coder maps the IP core to
mwipcore0 and uses channel
Address offset — Offset of register from base address of IP core
Enter the offset of the register from the base address of the IP core on the device.
The block writes data to this register. Use the
hex2dec function when you specify the address offset using a hexadecimal
number character vector.
Remote IP address — Network address of SoC device
192.168.1.101 (default) | valid URI string
Enter the network address of the connected SoC device.
To get a list of available IIO device names and channels, open a terminal to the Xilinx device, and execute this command:
Introduced in R2020b