HDL Coder Support Package for Xilinx Zynq Platform

Generate code for the FPGA portion of the Zynq SoC

HDL Coder™ Support Package for Xilinx^® Zynq^® Platform supports the generation of IP cores that can be integrated into FPGA designs using Xilinx Vivado^® or Xilinx ISE. When used in combination with Embedded Coder^® Support Package for Xilinx Zynq Platform, this solution can program the Xilinx Zynq SoC using C and HDL code generation. The hardware/software codesign workflow spans simulation, prototyping, verification, and implementation.

Setup and Configuration

Download and install support package for use with third-party EDA tools and supported hardware

Hardware-Software Co-Design Basics

Learn about the hardware-software co-design workflow and how to use the Workflow Advisor to run the algorithm on the SoC platform

Modeling

Model your algorithm in Simulink^® by using a simplified protocol for mapping to AXI4-Stream, AXI4-Stream Video, or AXI4 Master interfaces

Custom IP Core Generation

Generate HDL IP core from your DUT for deployment to the default system reference design or custom reference design registered with the board

Custom Board and Reference Design

Define and register custom reference design or custom board for Xilinx Zynq Platform

Deployment and Verification

Create bitstream containing user programming and download it to Xilinx Zynq Platform

HDL Coder Support Package for Xilinx Zynq Platform Documentation

Support

Deploying 5G NR Wireless Communications on FPGAs: A Complete MATLAB and Simulink Workflow

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