EtherCAT Distributed Clock Algorithm

An EtherCAT® network consists of a master node (the target computer) connected to an arbitrary number of slave nodes (devices). Each node contains a clock that controls its internal operation. When you enable distributed clocks, EtherCAT designates one clock in the network as the reference clock. The EtherCAT distributed clock (DC) algorithm then synchronizes the operation of multiple network nodes to the reference clock.

The DC algorithm operates in two phases. In phase 1, the algorithm aligns the clocks of DC-enabled network nodes other than the master node with the clock of the first DC-enabled slave node. In phase 2, the algorithm aligns the remaining unaligned clock with the reference clock.

Do not manually adjust the sample time of the real-time application in either master shift mode or bus shift mode.

Master Shift Mode

In master shift mode, the reference clock is the clock of the first DC-enabled slave in the network.

In phase 1, the algorithm shifts the sample time of the network nodes to align with the clock of the first slave node. In that process, the EtherCAT Init block output value NetworkToSlaveClkDiff decreases to near zero.

In phase 2, the algorithm shifts the sample time of the master stack running on the target computer to align with the first slave node clock. In that process, the EtherCAT Init block output value MasterToNetworkClkDiff decreases to near zero.

Bus Shift Mode

In bus shift mode, the reference clock is the clock of the master stack running on the target computer.

In phase 1, the algorithm shifts the sample time of the DC-enabled network nodes to align with the clock of the first DC-enabled slave node. In that process, the value NetworkToSlaveClkDiff decreases to near zero.

In phase 2, the algorithm shifts the sample time of the first DC-enabled slave node to align with the clock of the master stack. In that process, the value MasterToNetworkClkDiff decreases to near zero. The algorithm shifts the sample time of the other network nodes to stay aligned with the first slave node clock. In that process, the value of NetworkToSlaveClkDiff first increases, then decreases to near zero.

Limitations

If you configure EtherCAT distributed clocks in master shift mode, using the IEEE 1588 Sync Execution block in the same model produces a build error. To include EtherCAT distributed clocks and IEEE® 1588 synchronized execution in the same model, use EtherCAT bus shift mode.

See Also

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