FPGA Subsystem Plan

Before you work with the HDL Coder™ HDL Workflow Advisor, plan how to prepare the FPGA subsystem for HDL code generation and FPGA synthesis.

Target Device

First, to decide which FPGA to target for code generation, consult the Speedgoat data sheet for information:

  • Availability and cost

  • Bus compatibility

  • Size

  • Pinouts

  • Clock speed

The example procedure uses the Simulink® Real-Time™ FPGA workflow and the Speedgoat IO331 FPGA IO board as target platform. This choice requires that you use the Xilinx® ISE synthesis tool.

For information about other target devices, see Supported Third-Party Tools and Hardware (HDL Coder).

FPGA Synchronization Mode

To select the processor/FPGA synchronization mode, you must decide which of the FPGA synchronization modes to use:

  • Free running

  • Coprocessing — blocking

  • Coprocessing — nonblocking with delay.

For more information, see FPGA Synchronization Modes.

FPGA Inports and Outports

Inports and outports can transmit signal data between the Speedgoat target machine and the FPGA over the PCI bus. Alternatively, they can map to I/O channels for communicating with external devices. For connector pin and I/O channel assignments of your supported FPGA I/O board, see the board reference page for your board.

In addition to the Port Name and Port Type (Inport or Outport), to specify the I/O interface, see:

  • Data Type—Encodes such attributes as width and sign. Data types must map consistently to their corresponding I/O pins. An inport of type Boolean requires 1 bit, one of type uint32 requires 32 bits, and so on. For example, you cannot connect an inport of type uint32 to an FPGA I/O interface of type TTL I/O channel [0:7]; it requires TTL I/O channel [0:31].

  • Target Platform Interfaces—Encodes the I/O channels on the FPGA and their functional type. For a single-ended interface (TTL, LVCMOS), one channel maps to one connector pin. For a differential interface (RS422, LVDS), one channel maps to two connector pins. To discover the mapping for a particular pin, see the pin connector map provided with the board description.

    I/O channels can also map to a predefined specification or role (PCI Interface, Interrupt from FPGA).

    For information on using FPGA interrupts, see Interrupt Configuration.

  • Bit Range/Address/FPGA Pin—Encodes the pins on the target platform to which the inports and outports are assigned, along with the channel number used by the port. For specification PCI Interface, Bit Range/Address/FPGA Pin encodes the PCI address used by the port.

If vector inports or outports are required, specify a vector port:

  • Inport — Add a mux outside the subsystem that connects to a demux inside the subsystem.

  • Outport – Add a mux inside the subsystem that connects to a demux outside the subsystem.

  • Inport and Outport – Configure the port dimension to be greater than 1.

To achieve a simultaneous update of vector port elements, Workflow Advisor automatically inserts a strobe and specifies a strobe offset. For more information, see IP Core User Guide (HDL Coder).

If you have specified vector inports or outports, before generating code, you must select the Scalarize vector ports check box. This check box is on the Coding style tab of node Global Settings, under node HDL Code Generation in the Configuration Parameters dialog box.

FPGA Clock Frequency

The FPGA system clock frequency defaults to the fixed FPGA input clock frequency. The fixed FPGA input clock frequency is shown in the FPGA input clock frequency (MHz) box. You can specify another frequency in this box. If the FPGA clock circuits cannot generate the specified value exactly, HDL Coder HDL Workflow Advisor generates the closest match. The closest match, Fsystem, is based on the following formula:

Fsystem=Finput*ClkFxMultiply/ClkFxDivide

Finput is the fixed FPGA input clock frequency. ClkFxMultiply and ClkFxDivide are integers.

FPGA Deployment

The FPGA deployment procedure depends upon the FPGA model.

Deploy the IO321 and IO331 FPGAs

When HDL Coder HDL Workflow Advisor generates the programmed FPGA subsystem, it writes an SLX file (gm_mdlname.slx) and a C file (blkorrefmdlname_topiospeedgoat#.c) into the model folder. The SLX file contains the FPGA subsystem. The C file contains the bitstream.

For example, assume that model fpga_model.slx contains a Subsystem block named fpga_subsystem, and that you configure the FPGA target platform for the model as Speedgoat IO331. Then HDL Coder HDL Workflow Advisor generates the following files:

gm_fpga_model.slx
fpga_subsystem_topIO331.c

When you build your domain model with the integrated subsystem, the model builder:

  1. Reads the C file.

  2. Inserts its contents into the real-time application.

  3. Packages the real-time application as an MLDATX file.

The model builder assumes that the SLX file and the C file are in the same folder. If you deploy the model to another location on the disk, copy the SLX file and the C file to the new location.

Deploy the IO333 FPGA

When HDL Coder HDL Workflow Advisor generates the programmed FPGA subsystem, it writes an SLX file (gm_mdlname.slx) and an MCS file (blkorrefmdlname_timestamp.mcs) into the model folder. The SLX file contains the FPGA subsystem. The MCS file contains the bitstream.

For example, assume that model fpga_model.slx contains a Subsystem block named fpga_subsystem, and that you configure the FPGA target platform for the model as Speedgoat IO333. Then HDL Coder HDL Workflow Advisor generates the following files:

gm_fpga_model.slx
fpga_subsystem_201703301740.mcs

When you build your domain model with the integrated subsystem, the model builder:

  1. Generates the real-time application.

  2. Packages the real-time application and the MCS file as an MLDATX file.

The model builder searches for the MCS file on the MATLAB® path. If you deploy the model to another location on the disk, add the new location to the path.

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