Simulink® Real-Time™ and HDL Coder™ enable you to implement Simulink algorithms and configure I/O functionality on Speedgoat field programmable gate array (FPGA) boards.
For an example that shows the development workflow for FPGA I/O boards, see FPGA Programming and Configuration. You do not use these blocks outside of HDL Coder HDL Workflow Advisor.
To use these blocks, open HDL Coder HDL Workflow Advisor and use it to generate a Simulink Real-Time interface subsystem. See FPGA Programming and Configuration.
The subsystem mask controls the block parameters. Do not edit the parameters directly. The FPGA I/O board block descriptions are for informational purposes only.
Speedgoat I/O FPGA boards are sold as part of Speedgoat target computer systems. See:
Real-Time supports the following Speedgoat (
FPGA I/O boards.
The Speedgoat IO331 is a field-programmable gate array (FPGA) board that provides 64 bidirectional LVCMOS or 32 bidirectional LVDS I/O lines. This board is based on a Xilinx® Spartan® 6 chip with 147,333 logic cells.
The Speedgoat IO331 is the base board. The Speedgoat IO331-6 is the AXM-A75 A/D converter, an add-on to the Speedgoat IO331.
The Speedgoat IO333 is a field-programmable gate array (FPGA) board based on a Xilinx Kintex® 7 chip with 325k logic cells.
HDL Coder HDL Workflow Advisor supports the Speedgoat IO333-325K-06 configuration. For more information, see Speedgoat HDL Coder Integration Package for the IO333-325K at www.speedgoat.com/help.
To work with FPGAs in the Simulink Real-Time environment, you must:
Install HDL Coder and Xilinx design tools. For the specific tool and version required, see the board reference topic and the HDL Coder documentation.
Install the Speedgoat FPGA I/O board in the Speedgoat target machine.
Be familiar with FPGA technology. In particular, you must know the clock frequency and the I/O connector pin and channel configuration of your FPGA board.
Have experience using data type conversion and designing Simulink fixed-point algorithms.
To generate HDL code for your FPGA target, you do not need to have HDL programming experience.