Simulink® Real-Time™ software schedules the real-time application using either the internal timer of the Speedgoat target machine (default) or an interrupt from an I/O board. You can use your Speedgoat FPGA board to generate an interrupt, which allows you to:
Schedule execution of the real-time application based on this interrupt (synchronous execution). For this method, you must generate the interrupt periodically.
Execute a designated subsystem in your real-time application (asynchronous execution).
To use FPGA-based interrupts, set up and configure the FPGA domain and Simulink Real-Time domain models.
In the FPGA domain subsystem, create the interrupt source for the real-time application in one of the following ways.
A clock you create using Simulink blocks to create input signals. This clock is a binary pulse
train of zeros and ones (transition from
A clock signal that comes from a device outside the Speedgoat target machine. You use a digital input pin to connect to this signal. The following is an example of an externally generated interrupt source that comes from TTL channel 8. Delay this source by one FPGA clock cycle and connect to an outport labeled INT.
In both cases, wire the interrupt source to an outport in the FPGA subsystem. Assign the
Interrupt from FPGA in the HDL Coder™ HDL Workflow Advisor task 1.2 Set Target
You are now ready to set up interrupt support in the Simulink Real-Time domain model.
Configure the model Simulink Real-Time domain model to set up interrupt support:
Open the Simulink Real-Time domain model.
In the Simulink editor, select Simulation > Model Configuration Parameters.
Navigate to node Simulink Real-Time Options, under node Code Generation.
From the Real-time interrupt source list, select one of the following:
Auto (PCI only)
The IRQ assigned to your FPGA board
From the I/O board generating the interrupt parameter, select
your FPGA board, for example,
Add the Simulink Real-Time interface subsystem to the model.
Build and download the real-time application to the Speedgoat target machine.
When you start the real-time application, simulation updates occur when the application receives an interrupt from the FPGA I/O board.