PLL-Based Interrupt Generation from FPGA Input

This example shows how Simulink® Real-Time™ can drive a target application not only with interrupts based on its internal timer, but also with interrupts based on an external signal.

In the simplest use case, we would like to run the real-time application synchronized 1-1 to the external signal; for instance, every time we receive a rising edge from an external signal, an interrupt is generated which then runs one step of the application. Using a phase-locked loop (PLL), we can drive the real-time application at a frequency that is different from the input frequency, but at the same time synchronized to the external signal. For instance, we may have an external signal at 600 Hz, but we would like to run the application at 2 kHz.

This example uses a Speedgoat FPGA based I/O module (the Speedgoat IO331) and a digital PLL modeled in Simulink®. From the model, HDL Coder™ generates and synthesizes HDL code. You can use any FPGA I/O module supported by Simulink Real-Time and HDL Coder that meets the speed, size, and pinout requirements of the model.

Requirements and Preconditions

  • HDL Coder™

  • DSP System Toolbox™

For the IO331 board, HDL Workflow Advisor requires the Xilinx® ISE toolset. To install this toolset, in the Command Window, type:

hdlsetuptoolpath('ToolName', 'Xilinx ISE', 'ToolPath', toolpath)

where toolpath is the full path to the synthesis tool executable.

For the toolset requirements of other boards, see Supported Third-Party Tools and Hardware (HDL Coder).

PLL and frequency synthesis

A PLL is required to lock the generated frequency since the desired frequency is any arbitrary ratio (synN/synM, within some range) of the input frequency. We will first create a model with the PLL in the 'Frequency synthesis' subsystem. The model contains top level blocks that aid the simulation of the model on the desktop as well as provide inputs to the FPGA in order to tune parameters while running in real-time on the target.

An external signal of frequency Fr is input into one of the TTL I/O lines configured as input. We wish to drive the model at a frequency . synN and synM are integers that may be varied to obtain frequencies different from Fr. The model dslrtExtDIOInt uses a phase-locked loop (PLL) to lock the frequency generated by the NCO HDL Optimized block to the desired frequency Fd.


Frequency synthesis

The Frequency synthesis subsystem consists of a Phase detector subsystem, a numerically controlled oscillator (NCO) and frequency dividers. HDL code will be generated for this subsystem.

Phase Detector

The phase detector subsystem compares the phase of two signals by using an XOR block. The 'countDutyCycle' function block implements a loop filter in the form of counting the number of high samples between two rising edges of the XOR output. It also compares the occurrence of the rising edges of the two input signals to the subsystem in order to provide a sign to the phase difference.

Transfer function of the 'countDutyCycle' function:

x = [-5/4 -1 -(1/2+eps) -1/2 0 1/2 (1/2+eps) 1 5/4];
y = [   -.5  0      1          -1  0  1       -1     0     .5];
h = plot(x,y);
a=get(h, 'parent');
a.XTickLabel = {  ''   '-\pi'   '-\pi/2'  '0'  '\pi/2' '\pi' ''};
a.YTick = [-1 0 1];
a.YTickLabel = {'-N' '0' 'N'};
a.XGrid ='on';
a.YGrid ='on';
xlabel('Phase difference (rad)');
ylabel('Output (Duty cycle in number of samples)');
title('Phase Detector output');

The phase detector output wraps around outside of the range indicating the working range of the XOR detector. Due to this the input frequency should be within a certain working range of the PLL. The value N on the y-axis depends on the instantaneous frequency of the input signal and the center frequency Fc. The range is derived in the section 'PLL working frequency range'.

NCO HDL Optimized: The numerically controlled oscillator generates a quiescent frequency as determined by the input 'Center freq'. When the input signal 'Ref In' varies from the center frequency, the 'Phase Detector' output generates a signal to make up for the difference in frequency. The generated correction signal is added to the value for the center frequency to produce the appropriate frequency. This subsystem is used only for debugging and monitoring and can be safely left out of the application.

Frequency Dividers: These divide the frequency of the square wave input into 'Ref In' and the generated signal to produce the required frequency transformation.

'Print Target Frequency' subsystem

This subsystem contains blocks which determine the time interval between consecutive sample hits and prints the instantaneous model execution frequency in kilohertz. For accurate measurement the block 'CPU Clk Freq' should be set to the CPU clock frequency of the target divided by 1e3 (for conversion to kHz).

PLL working frequency range

The following is a list of variables and default values used by the model (defined in the PreLoadFcn model callback):

   synN = 3;       % frequency division ratio
   synM = 2;       % frequency division ratio
   Fs = 33e6;      % Sampling Frequency
   Fr = 16.5e3;    % Input frequency = 16.5 kHz
   df = .5;        % Frequency resolution = .5 Hz
   minSFDR = 96;   % Spurious free dynamic range >= 96 dB
   Ts = 1/Fs;                  % Sample period = 3.0303e-08 seconds
   Fc = Fr * synN / synM;      % Oscillator Center frequency = 24.75 kHz
   % For simulation only:
   inputPeriod = round(Fs/Fr);
   % Ensure period is even for the pulse generator to produce 50% duty cycle
   inputPeriod = inputPeriod + mod(inputPeriod, 2);
   % 'Period' parameter of Pulse Generator block = 1334
   % Calculate number of accumulator bits required for the frequency resolution.
   Nacc = ceil(log2(1/(df*Ts))); % NCO Accumulator word length = 26
   actdf = 1/(Ts*2^Nacc); % Actual frequency resolution achieved = 0.4917 Hz
   % Calculate number of quantizer accumulator bits required from the SFDR requirement.
   Nqacc = ceil((minSFDR-12)/6); % number of quantizer accumulator bits = 14
   % Calculate the phase increment.
   inc = round(Fc*Ts*2^Nacc); % inc = 75497

The working range of this PLL may be derived as follows:

The limits at - /2 and /2 are reached when the delay in the generated signal corresponds to half the number of samples in one period of the signals. This can occur at a frequency and above and below the center frequency, respectively. Consider the lower frequency . To simulate this frequency using the pulse generator block the variable 'inputPeriod' needs to be increased by a value 'x'. As a result:

The Phase Detector produces an output equal to the duty cycle within the range or one period of the square wave being compared. The correction factor = . This is combined with the phase increment value corresponding to the center frequency to produce the frequency equal to the input. Equating the two previous results gives:

Solving this quadratic equation and taking the smaller root gives from which is calculated:

   x_l = min(roots([1 -(inc - (2*inputPeriod)) - (inputPeriod*(inc - inputPeriod)) + (2^Nacc*(synN/synM))]));
   % The lower bound for the frequency range is:
   Fl = Fs / (inputPeriod + x_l);

Similarly the upper frequency bound may be calculated:

   x_h = min(roots([1 -(inc + (2*inputPeriod)) +(inputPeriod*(inc + inputPeriod))-(2^Nacc*(synN/synM))]));
   % The upper bound for the frequency range is:
   Fh = Fs / (inputPeriod - x_h);

Open the model

Click here to open the model: dslrtExtDIOInt.

Generate HDL Code using HDL Workflow Advisor

For this example the device used is a Speedgoat IO331 FPGA board. The HDL code generation procedure is as described in the example Digital I/O with Speedgoat FPGA Board. The differences include the board used and the input and output pin mappings which are described in this section.

Target Device

Set the target platform to the Speedgoat IO331 FPGA and check that HDL Workflow advisor sets the synthesis tool to the Xilinx® ISE Design Suite. This setting configures the board characteristics and synthesis tool used in subsequent tasks.

Target interface

The reference signal is input at the first pin (pin 0). The NCO output is mapped as the 'Interrupt from FPGA'. This signal becomes the interrupt for driving the model execution on the CPU.

Target Frequency

The model is designed using a fixed step size corresponding to a sampling frequency of 33 MHz. Set 'Target Frequency' to this value. This is the frequency at which the 'Frequency synthesis' subsystem will run on the FPGA.

Generate FPGA Model

The model generated by HDL Workflow Advisor is now ready to be built and downloaded to the target. However, since the intention is to run the real-time application around the center frequency Fc it is appropriate to change the sample time of the generated model to 1/Fc before building and downloading. This may be done by executing:

   Ts = 1/Fc;

After you have set Ts:

  1. In the Simulink Editor, open the Configuration Parameters. On the Real-Time tab, click Hardware Settings.

  2. Select Code Generation > System target file to grt.tlc.

  3. Right-click Download to Target > Generate Simulink Real-Time Interface, and then click Run to selected task.

This action produces a generated model, gm_dslrtExtDIOInt_slrt.

Model Configuration Parameters

In the Configuration Parameters dialog box of the generated model, configure the target computer to be driven by the FPGA board interrupt:

  1. In the Simulink Editor, open the Configuration Parameters. On the Real-Time tab, click Hardware Settings.

  2. Select Code Generation > System target file to slrt.tlc.

  3. Set Simulink Real-Time Options > Real-time Interrupt source to Auto (PCI only).

  4. Set I/O board generating the interrupt to Speedgoat IO331.

You can now build and download the generated model to the target computer as a real-time application.

Model Execution

The values used in this example cause the input frequency to be centered at 16.5 kHz. The target scopes show the correction signal and the instantaneous frequency when the input signal frequency is increased from 16 kHz to 17 kHz. The real-time application is being executed at a frequency that is close to .

  • This model is able to handle only square pulses that have an approximate duty cycle of 50%.

  • The operation of the PLL is valid only in the frequency range as derived in the earlier sections.

bdclose all;