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Why is my FFT HDL Optimized block running slower in FIL than Simulink?

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I am trying to run a FFT model on a Basys3 FPGA board using HDL Coder from Matlab. I am using the FPGA-in-the-loop application to send data to FPGA board, which is programmed with a FFT, through JTAG. The implementation is working accurately, but the execution time is much more than running the same FFT model in Simulink directly. I am using Simulink Profiler to find the simulation time.

Accepted Answer

Bharath Venkataraman
Bharath Venkataraman on 22 Feb 2022
This slowdown is due to the time it takes to send the data over from Simulink to the FPGA and back.
You can use an Ethernet cable to speed up the conenction.
Another option is to feed and receive multiple samples at a time as shown in this example. So for an FFT size of 256, you can send in the 4 values (as you do currently), but 64 samples in at a time. The valid input signal will also need to be 64x1. In turn, you will get 64 output values for each call.
The simplest way to do this is by use of a Buffer block before each input. In this case, you may be able to modify your source to do this as well.
Bharath Venkataraman
Bharath Venkataraman on 23 Feb 2022
Edited: Bharath Venkataraman on 24 Feb 2022
Thank you for the clarification.
The purpose of the FIL block is verification and not necessarily speed of execution. So for your specific model, you may just find that running the Simulink model is faster than FIL. A bigger different model may yield a different result. For smaller models, the speed of the link is likely to be the bottleneck.
As I mentioned in a previous response, you could also get a faster link (ex. Ethernet) to the board and also pipe in more samples at a time to the board to see how much faster the FIL simulation can go.
Adil Zafar
Adil Zafar on 23 Feb 2022
OK. Thank you so much for the responses. Really cleared things up for me.

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