HDL Verifier: Why do I observe a lower order bit resolution in 256-bit fixed-point cosimulation signals between Questasim 2022.4 and MATLAB R2025a?

I am using the HDL Verifier Cosimulation feature with Questasim 2022.4 and MATLAB R2025a to simulate VHDL code generated by HDL Coder from a Simulink model. My Design Under Test (DUT) includes a top-level input signal to the "HDL Cosimulation" block that is a 256-bit fixed-point data type. When running the simulation, I observe that the value of this input signal as seen inside the RTL simulator (Questasim) does not match the value sent from Simulink; specifically, the lower-order bits appear to be incorrect, indicating a loss of resolution or data truncation.

For example, the input value observed in Simulink does not match the value observed in Questasim, as shown below:

0x0001000000000000000000000000010300000000000000000000002007800000 (input value as shown in Simulink) 
0x0001000000000000000000000000010300000000000000000000002000000000 (input value as shown in the RTL simulator)

Is this a precision issue or a model issue? Is there a resolution or workaround for this issue?

Answer 1

[MathWorks Support Team]

This issue occurs because the "HDL Cosimulation" block currently does not support native fixed-point types with a word length greater than 128 bits. Support for wider fixed-point types introduced in recent releases has not yet been fully integrated into all related products.

That said, the "HDL Cosimulation" block does support vectors, provided that each element has a word length of 128 bits or less. This capability enables the representation of signals wider than 128 bits by using a vector of smaller elements. Therefore, a recommended workaround would be to use "Bit Slice" blocks to partition the 256-bit signal into a vector of 128-bit signals within the generated cosimulation model, by extracting bits 255 (MSB) down to 128 (LSB) in one block and bits 127 (MSB) down to 0 (LSB) in the other. The resulting signals can then be combined into a vector using a “Mux” block.

For more information on how vectors are mapped to HDL signals, see the “Simulink Word Length” section in the "HDL Cosimulation" MATLAB documentation page.