How to create a single dsp model that can be used for different fpga vendors (HDLcoder)

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Hi All,
First of allmy background is based on pure VHDL and what I would normally do is create different architectures for different vendors and or device famliy and have on top entity which uses a variant based on generics.
Since I just get to know Matlab/Simulink I was wondering if I could use a similar approach in simulink based on the family options you can choose in the HDL coder settings but I can not seem to figure it out.
I think I need to use a variant subsystem? It would be very helpfull if someone could point me into the right direction? Maybe someone has a simple example how to code for different vendors?
Btw I tried to use the "optimized" multiply-add blocks which came with matlab but they don't work like i would expect.
Best Regards,

Accepted Answer

Kiran Kintali
Kiran Kintali on 10 Aug 2021
You can generate HDL code from variants. Attached is an example of the variant subsystem model using basic variant features.
You can create them using the documentation here
If you would like to connect the variant controls to the model HDL settings, you can use the command line API
hdlget_param(<modelname>, 'HDLOption')
Here are the sample settings stored on the model
>> hdlsaveparams('slow_fast_counter_variant/top')
%% Set Model 'slow_fast_counter_variant' HDL parameters
hdlset_param('slow_fast_counter_variant', 'HDLSubsystem', 'slow_fast_counter_variant');
hdlset_param('slow_fast_counter_variant', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('slow_fast_counter_variant', 'SynthesisToolChipFamily', 'Artix7');
hdlset_param('slow_fast_counter_variant', 'SynthesisToolDeviceName', 'xa7a100t');
hdlset_param('slow_fast_counter_variant', 'SynthesisToolPackageName', 'csg324');
hdlset_param('slow_fast_counter_variant', 'SynthesisToolSpeedValue', '-1I');

More Answers (1)

Kiran Kintali
Kiran Kintali on 5 Aug 2021
>> But it won't load in my matlab version R2019b
>> openExample('hdlcoder/DesignForEfficientDSPBlockMappingExample')
Attached 19b version of the example, but recommend upgrading to latest release to take advantage of new HDL Coder features. https://www.mathworks.com/help/hdlcoder/release-notes.html
>> what I would normally do is create different architectures for different vendors and or device famliy...
HDL Coder generates synthesizable HDL and supports multiple FPGA vendors and ASIC.
If you feel there is need to create multiple variants of the same logic you can use of variants subsystems or model references for specific variations that you have in mind.
  2 Comments
Lars Willeboordse
Lars Willeboordse on 10 Aug 2021
Hi Kiran Kintali,
Thank you for the reply and the example.
If I select the blocks provided by HDLcoder and select the correct family and vendor before generating the HDL I get synthesable code but it will not be implemented fully in dsp logic.
Therefore I was thinking I model the DSP slices myself for each family and use a variant subsystem for then. That way i will keep one design and "toplevel" if that makes sense.
I'd prefer to map those variant subsystem to the device family chosen in the GUI. Is that possible and do you have maybe an example on how to do this?
Best regards

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