FPGA Implementation of the Gray Scale Image Erosion Morphological Operation using HDL coder

Image Erosion operation has been implemented on gray scale image using HDL coder

In this submission a basic image morphological operation called "Erosion" has been implemented using HDL coder.The implementation has been done using Gray scale image.The main motivation behind this work is to generate FPGA programmable bit file for programming the concerned FPGA board(in this case virtex-ML507 has been used).The generated vhdl code has been successfully simulated using ModelSim-10.1c and synthesized using Xilinx Virtex-ML507.In the synthesized system the clock frequency of 335.171 MHz has been achieved.