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HDL Verifier SystemVerilog DPI component generation with Synopsys VCS

version 1.0.0.0 (1.42 MB) by Jack Erickson
Generate SystemVerilog DPI component from MATLAB for Synopsys VCS simulation

8 Downloads

Updated 14 Jul 2017

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This example was used in the video demonstration:
https://www.mathworks.com/videos/generate-systemverilog-dpi-components-for-simulation-with-synopsys-vcs-1495725854304.html
It illustrates how to re-use MATLAB functions and stimulus to more quickly build a Universal Verification Methodology testbench. Specifically it generates SystemVerilog DPI components from a MATLAB algorithm for use in a UVM scoreboard, and for a realistic video input for use as a UVM sequence item. The simulation is set up to run Synopsys VCS.

Cite As

Jack Erickson (2020). HDL Verifier SystemVerilog DPI component generation with Synopsys VCS (https://www.mathworks.com/matlabcentral/fileexchange/63335-hdl-verifier-systemverilog-dpi-component-generation-with-synopsys-vcs), MATLAB Central File Exchange. Retrieved .

Comments and Ratings (1)

Ryan Hawl

MATLAB Release Compatibility
Created with R2017a
Compatible with any release
Platform Compatibility
Windows macOS Linux

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