Voltage Sag and Swell Caused by LL Fault

by wawa

The Simulink model circuit here is how to create a line fault model. The type of fault used is LL fault occurs at phase A and B. There'll be 2 waveform produced which are the load voltage(Vload) and RMS load voltage(Vload_RMS) presented for a better voltage sag and swell analysis. The fault occurs at 0.1s till 0.15s.

It can be observed that the load voltage sags at phase A and phase B happeed due to high fault resistance of 8 Ω between the two faulted lines whilst, the unfaulted phase C experiences a slight voltage swell due to the absent of ground point in the line-to-line fault and high fault resistance.

Please open the link below to see how to mitigate the voltage sag by using DVR:
https://www.mathworks.com/matlabcentral/fileexchange/77317-mitigation-of-volt-sag-by-using-dvr-w-pi-and-fl-controller