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Bharath Venkataraman


Last seen: 2 days ago

MathWorks

187 total contributions since 2013

Bharath Venkataraman's Badges

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Answered
Implementation of median filter on FPGA
Are you able to generate VHDL (which is the default), or is there an error during HDL code genration? The last section (Generat...

2 days ago | 0

Answered
Implementation of median filter on FPGA
Here is a link to an example of how to do this in Simulink.

8 days ago | 0

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Answered
converting a vector input to scalar
The Signal From Workspace block should help you get your data into Simulink. https://www.mathworks.com/help/dsp/ref/signalfromw...

16 days ago | 0

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CRC generation in HDL
You can set the CRC polynomial on the block and send in the bits either serially or multiple bits at a time based on your polyno...

2 months ago | 0

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How to speed up a Simulink simulation of slow mechanics requiring a fast clock?
There are a wide variety of things you can do. The first thing to try is to run the model in Accelerator or Rapid Accelerator mo...

6 months ago | 0

Answered
Cosimulation Wizard and required toolboxes
You need the HDL Verifier product to use the Cosimulation Wizard.

7 months ago | 0

Answered
HDL Coder - reducing size of fixed-point variables
The number of bytes taken to store the fixed-point variable in MATLAB does not determine the number of bits in HDL. te number of...

7 months ago | 0

Answered
Generating VHDL code from MATLAB program using HDL generator
Is there a pattern to how x gets its value that you can utilize here? For example, if x is incremented by 1 all the time, or onl...

7 months ago | 0

Answered
"Abnormal exit: Can't find bus object 'pixelcontrol' in the MATLAB workspace" error in HDL Coder
Please try running the command pixelcontrolbus in the MATLAB command line.

7 months ago | 0

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Answered
Why i do not get a fixed point out from a FFT HDL optimized block in simulink?
I may need the model to do further debugging. In the meantime, I created a simple FFT model in R2018b which seems to do the righ...

7 months ago | 1

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Answered
Why i do not get a fixed point out from a FFT HDL optimized block in simulink?
Could you double click on the FFT block and send a snapshot of its parameters?

7 months ago | 0

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HDL Coder doesn't create input for clock signal
Does your MATLAB code have states? You need to have some state in the MATLAB code to have resets and clocks. This is an example...

7 months ago | 0

Answered
What values to use for minimum blancking for a pixel streaming interface
Typical video interfaces (240p and higher resolution) will have sufficient blanking, so one way to go is to pick blanking requir...

8 months ago | 0

Answered
VariableSizeFFTHDLExample File Not found
The LTE HDL Toolbox product is required for this example.

8 months ago | 0

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Answered
How to read an image in a simulink
Please look at the examples in Vision HDL Toolbox to see how to go about doing this. https://www.mathworks.com/help/visionhdl/e...

8 months ago | 0

Answered
使用Generate HDL Code from MATLAB Code Using the Command Line Interface时,显示错误使用 codegen
It appears that you need to set up the path to ISE. See teh function hdlsetuptoolpath for information on how to do this.

9 months ago | 0

Answered
Differences in Performance Between Simulink and Matlab FIRs
Attached is a model where I have taken your coefficients and ran them through fitler and the FIR Filter block. The numbers seem ...

9 months ago | 0

Answered
Differences in Performance Between Simulink and Matlab FIRs
Could you please pass along a complete script that runs? I think Fs=30e6 from your comments, but I do not have data defined.

9 months ago | 0

Answered
Differences in Performance Between Simulink and Matlab FIRs
I suggest using the the Discrete FIR Filter block with the coefficients you used for MATLAB. If that works, it is the easiest wa...

9 months ago | 0

Answered
How to use boolean to control switch with fixed point data.
S1 and S2 when they are assigned to mealy_state_reg likely need to be fixed point. Try using assignements as follows: mealy_st...

9 months ago | 0

Answered
RTL generation error: Signal rate of value inf found
If you turn on sample time colors in your model, you should be able to see where the inf sample time is being set.

9 months ago | 0

Answered
can someone please help about NCO HDL optimized block. How to generate a simple sine wave with it. I am gettting a single straight line as output for what ever phase increment i use. can someone help how to set sampling frequency as well
Attached is a simple NCO which generates a sine wave. Phase increment is set to 4 and accumulator size is 8 bits, so you will se...

10 months ago | 0

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Answered
How to use a vector of complex data as source in HDL coder?
Attached is a simple model that shows how to stream in a 4 value complex vector one value at a time. The values are split into r...

10 months ago | 0

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Answered
HDL code to simulink model
You can use an HDL Cosimulation block to import this into Simulink. Here is a video and documentation for the procedure.

10 months ago | 0

Answered
How to generate HDL serial filter architecture form Digital Down-Converter example
It does not apply to the CIC, please try it for the FIR Filter.

10 months ago | 0

Answered
How can I figure out how many delay units do I need in one part of Simulink HDL design?
One of the ways to do this is by logging the input and output signals to the Logic Analyzer. You can set your cursors on the inp...

10 months ago | 0

Answered
How to generate HDL serial filter architecture form Digital Down-Converter example
You can take each of the filters through the process of HDL code generation to control how many resources to use. To do so, run ...

10 months ago | 0

Answered
Problem Using/Doing FFT HDL Optimized
Please take a look at this example which shows how to use the HDL Optimized FFT block.

10 months ago | 0

Answered
HDL Coder disable Clock Enable output port
There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on th...

11 months ago | 0

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Answered
HDL Coder disable Clock Enable output port
You can use the option Minimize Clock Enables to remove the clock enable port. The clock enable typically cannot be removed for ...

11 months ago | 0

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