FPGA and ASIC Design with HDL Coder and HDL Verifier
Generate HDL Code from MATLAB and Simulink
You can generate synthesizable HDL code for FPGA and ASIC implementations in a few steps:
- Model your algorithm, including finite-state machines and datapath elements, using MATLAB® and Simulink®.
- Optimize models to meet speed-area-power objectives for FPGA or ASIC design using methods such as resource sharing (folding) and distributed pipelining.
- Generate HDL code using HDL Coder.
- Prototype on FPGAs and automate HDL verification using HDL Verifier.
Generate HDL Code from MATLAB
Using HDL Coder, you can automatically convert MATLAB code from floating point to fixed point and generate synthesizable VHDL and Verilog code. With this capability, you can model your algorithm at a high level using MATLAB constructs and System objects while utilizing options for optimizing generated HDL code. You can use the library of ready-to-use logic elements, such as counters and timers, which are written in MATLAB.
Generate HDL Code from Simulink
You can use HDL Coder to generate VHDL and Verilog code from Simulink and Stateflow®. With Simulink, you can model your algorithm using a library of more than 200 blocks. This library provides complex functions, such as the Viterbi decoder, FFT, CIC filters, and FIR filters, for modeling signal processing and communications systems and generating HDL code. You can use HDL Coder for IP core generation targeting Intel and Xilinx FPGAs and SoC FPGAs.
Prototype on FPGAs
Using HDL Coder, you can program FPGAs, including devices from Intel®, Xilinx®, and Microsemi®. This capability helps you quickly prototype your design on FPGA hardware. The Workflow Advisor in HDL Coder integrates with Xilinx ISE® and Intel Quartus® II design suites to automatically program your FPGAs from within MATLAB and Simulink.
You can use HDL Coder to prototype your algorithm on a variety of Xilinx, Intel, and Microsemi FPGA development boards. Additionally, you can use target-independent HDL code to program devices from other FPGA vendors such as Lattice Semiconductor®. You can also retarget code generated by HDL Coder to ASICs (8:56) , and use HDL Verifier to verify the ASIC implementation corresponds to the Simulink model.
Automate HDL Verification
You can reuse your MATLAB and Simulink testbench to verify your HDL code using cosimulation and FPGA-in-the-loop functionality provided by HDL Verifier. FPGA-in-the-Loop is supported for a large number of predefined boards from Xilinx, Intel, Microsemi, Avnet® and Arrow Electronics®, and may be extended to additional FPGA boards using FPGA Board Customization.
When used with HDL Verifier, HDL Coder automatically generates cosimulation and FPGA-in-the-loop models to accelerate the workflow for FPGA or ASIC design verification. This approach eliminates the need to manually transfer test vectors and helps identify errors earlier in the ASIC design process.
HDL Verifier exports your MATLAB algorithm or Simulink subsystem for use in functional verification environments, including those that use the Universal Verification Methodology (UVM). Using MATLAB Coder™, Simulink Coder™, or Embedded Coder®, HDL Verifier generates a C model with a SystemVerilog Direct Programming Interface (DPI) for behavioral simulation in your EDA simulator. This capability enables you to reuse your MATLAB algorithms and Simulink models in simulation as test sequence items, reference models, scoreboards, or system environment models.