From Model to Silicon: Efficient Digital Filter Design and Hardware Implementation
Overview
MATLAB® and Simulink® are de facto industry-standard tools for digital filter design, but how do you transition from algorithmic models into high-performance, resource-efficient RTL implementations? In this webinar, we will present a hands-on, tutorial-style workflow that guides you through the process from initial filter specifications through to verified RTL code.
You will learn how to architect, analyze, and simulate different classes of filters, evaluate trade-offs in fixed-point precision, and apply hardware-oriented optimizations to meet performance, area, and power constraints. The workflow emphasizes traceability from high-level models to synthesizable HDL, using hardware-aware techniques for optimized implementation.
Real-world applications such as a 64-QAM transmitter/receiver and a vision subsystem for lane detection—will be used to demonstrate modeling an algorithm together with this environment with which it interacts. The session also highlights the use of pre-verified Simulink blocks and System objects to accelerate development and enforce best practices in creating hardware-friendly, reusable architectures.
About the Presenter
Tom Henige supports customers in adopting MathWorks HDL code generation and verification products. He brings more than 20 years of experience in FPGA design and verification, with a background that includes next-generation wireless systems at Samsung Research America, aerospace communications and telemetry at Southwest Research Institute, and data acquisition systems at Texas Instruments. Tom holds a B.S. in Electrical Engineering from Texas A&M University and is an inventor on multiple patents in channel coding hardware design.
This event is part of a series of related topics. View the full list of events in this series.
