Deep Learning HDL Toolbox

 

Deep Learning HDL Toolbox

Prototype and deploy deep learning networks on FPGAs and SoCs

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Deep Learning HDL Toolbox provides functions and tools for prototyping and implementing deep learning networks on FPGAs and SoCs. It provides prebuilt bitstreams for running deep learning networks on supported FPGAs and SoCs (with SoC Blockset for AMD devices and HDL Coder for Altera devices). Profiling and estimation tools enable you to customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.

You can use the toolbox for customizing the hardware implementation of your deep learning network. Also, you can generate portable, synthesizable Verilog®, SystemVerilog, and VHDL® code for deployment on any FPGA or SoC devices (with HDL Coder and Simulink).

Screenshots of prototyping and implementing deep learning networks on FPGAs for edge deployment.
Block diagram of the toolbox’s programmable deep learning processor.

Perform FPGA-Based Inferencing of Networks

Use a programmable deep learning processor that features generic deep learning layers controlled by scheduling logic to perform FPGA-based inferencing of networks (with Deep Learning Toolbox). 

Documentation | Examples

Detection of a white truck with a bounding box.

Compile and Deploy Networks

Compile a deep learning network into a set of instructions to be run by the deep learning processor. Deploy your network to the FPGA and run predictions while capturing actual on-device performance metrics. 

Documentation | Examples

Photos of three different circuit boards with electronic components, connectors, and chips.

Get Started with Prebuilt FPGA Bitstreams

Rapidly prototype long short-term memory (LSTM) networks using available prebuilt bitstreams. Customize bitstream configurations to meet resource utilization requirements.

Examples (AMD | Altera)

Code snippet with a Xilinx bitstream, shown connected to an FPGA development board.

Deploy Networks to FPGAs

Use Deep Learning Toolbox to develop RNN and CNN networks or import a network. Then use the deploy function to program AMD FPGAs (with SoC Blockset) or Altera FPGAs. 

Documentation | Examples

Using MATLAB while loop calling the predict function.

Run FPGA-Based Inferencing in MATLAB Applications

Run a complete application in MATLAB, including your testbench, preprocessing and post-processing algorithms, and FPGA-based deep learning inferencing. A single function, predict,  performs the inferencing on the FPGA and returns results to the workspace in MATLAB. 

Examples

Profile FPGA Inferencing and Tune Network Designs

Using profile metrics, tune your network configuration by measuring layer-level latency as you run predictions on the FPGA to find performance bottlenecks.

Documentation

Compress Networks for FPGA Deployment

Compress Networks for FPGA Deployment

Reduce resource utilization by compressing your deep learning network with quantization and pruning. Analyze tradeoffs between accuracy and resource utilization using the Deep Learning Toolbox Model Compression Library support package.

Deep Learning Toolbox Model Compression Library

Documentation | Examples

Customize the Deep Learning Processor Configuration

Specify hardware architecture options for implementing the deep learning processor, such as the number of parallel threads or maximum layer size.

Documentation | Examples

Screenshot of custom bitstream coding.

Generate Synthesizable RTL and IP Cores

Use HDL Coder to generate synthesizable RTL from the deep learning processor. Generate IP cores with standard AXI interfaces for integration into  AMD and  Altera SoC designs.

Documentation | Examples

Product Resources:

Documentation Examples Videos Functions Hardware support Requirements Release notes

Deep Learning HDL Toolbox FAQs

Deep Learning HDL Toolbox provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs, offering prebuilt bitstreams for running networks on supported AMD (with SoC Blockset) and Altera devices.

The toolbox supports AMD (with SoC Blockset) and Altera FPGA and SoC devices with prebuilt bitstreams available for deployment.

Yes, you can program an FPGA using the deploy function and run inferencing using the predict function, without writing HDL code directly.

You can specify hardware architecture options such as the number of parallel threads or maximum layer size, and use profiling tools to explore design, performance, and resource utilization tradeoffs.

Yes, with HDL Coder and Simulink, you can generate portable, synthesizable Verilog, SystemVerilog, and VHDL code, as well as IP cores with standard AXI interfaces for SoC integration.

Quantization is optional but can reduce resource utilization. You can compress networks using pruning, projection, and quantization with the Deep Learning Toolbox Model Compression Library support package.

You can use profiling tools to capture actual on-device performance metrics, measure layer-level latency, and identify performance bottlenecks while running predictions on the FPGA.

You can deploy CNN and RNN networks, including LSTM networks, developed in Deep Learning Toolbox or imported from other sources.

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