Supported EDA Tools and Hardware

R2026b

Tool Support

Use this support package with:

  • Altera® Quartus® Prime Standard 24.1

  • Altera Quartus Prime Pro 25.3 (supported for Intel® Arria® 10, Cyclone® 10 GX, and Intel Agilex® 7 only)

For tool setup instructions, see hdlsetuptoolpath.

See also HDL Language Support and Supported Third-Party Tools and Hardware.

Board Support

When you install the HDL Coder™ Support Package for Intel FPGA and SoC Devices, you can target these boards:

Device FamilyBoardIP Core GenerationSoC Modeling and GenerationFPGA Verification and DebugDeep LearningAvailable Reference Designs

Arria 10 SoC

Altera Arria 10 SoC development kit

✓✓✓✓

Default System

Default system with External DDR4 Memory Access

Cyclone V

Cyclone V SoC development kit - Rev.C

✓✓✓ 

Default System

Cyclone V SoC development kit - Rev.D

✓✓✓ 

Arrow SoCKit development board

✓ ✓ 

Arria 10

Arria 10 GX FPGA development kit

✓ ✓ 

PCIe AXI Manager with External DDR4 Memory Access

JTAG AXI Manager with External DDR4 Memory Access

Altera MAX® 10

Arrow® DECA MAX 10 FPGA evaluation kit

✓ ✓ 

Default System

IP Core Generation Workflow with Ethernet-Based AXI Manager

Note

To extend support to new hardware, see Deploy IP Core on Custom Hardware.

You can add support for custom boards. For more information, see Board and Reference Design Registration System.

FPGA Board Connections

JTAG Connection

You can run FPGA-in-the-loop, FPGA data capture, or AXI manager over a JTAG cable to your board. However, each feature requires exclusive use of the JTAG cable, so you cannot run more than one feature at the same time. To allow other tools access to the JTAG cable, such as programming the FPGA, you must discontinue the JTAG connection in MATLAB®. To release the JTAG cable:

  • FPGA-in-the-loop — Close the Simulink® model, or call the release method of the System object™.

  • FPGA data capture — Close the FPGA Data Capture tool, release the System object, or close the Simulink model.

  • AXI manager — Call the release method of the object.

However, the nonblocking capture mode enables you to simultaneously use FPGA data capture and AXI manager, which share a common JTAG interface. For more information, see Simultaneous Use of FPGA Data Capture and AXI Manager.

The JTAG clock frequency depends on the type of cable and the maximum clock frequency supported by the FPGA or SoC board.

Required HardwareRequired SoftwareJTAG Clock Frequency

USB Blaster I or USB Blaster II download cable

  • USB Blaster I or II driver.

  • For Windows® operating systems: Quartus Prime executable directory must be on system path.

  • For Linux® operating systems: versions below Quartus II 13.1 are not supported. Quartus II 14.1 is not supported. Only 64-bit Quartus is supported. Quartus library directory must be on LD_LIBRARY_PATH before starting MATLAB. Prepend the Linux distribution library path before the Quartus library on LD_LIBRARY_PATH. For example, /lib/x86_64-linux-gnu:$QUARTUS_PATH.

12 or 24 MHz

Note

When simulating your FPGA design through JTAG cable with Simulink or MATLAB, you cannot use any debugging software that requires access to JTAG, such as Altera SignalTap II.

Ethernet Connection

You can run FPGA-in-the-loop, FPGA data capture, or AXI manager over an Ethernet connection. To use FPGA data capture and AXI manager over an Ethernet connection in a single HDL project, connect the FPGA data capture and AXI manager IPs to the same Ethernet MAC Hub IP using different port addresses.

Required HardwareSupported Interfaces Required Software

  • Gigabit Ethernet card

  • Cross-over Ethernet cable

  • FPGA board with supported Ethernet connection

  • SD card (for Intel Agilex 7 SoC device)

  • Gigabit Ethernet — GMII

  • Gigabit Ethernet — RGMII

  • Gigabit Ethernet — SGMII

  • Ethernet — MII

  • Ethernet — RMII

There are no software requirements for an Ethernet connection, but ensure that the firewall on the host computer does not prevent UDP communication.

Note

  • FPGA data capture and AXI manager support GMII, MII, and SGMII interfaces only.

  • AXI manager in HDL Workflow Advisor supports programmable logic (PL) Ethernet only. PS Ethernet is not supported.

  • FPGA data capture in HDL Workflow Advisor supports the GMII and MII interfaces. The SGMII interface is not supported.

PCI Express Connection

FPGA-in-the-loop over a PCI Express® connection is supported only for 64-bit Windows operating systems.

PCI Express connection for FPGA-in-the-loop and AXI manager is supported for Quartus II 15.0 or newer versions.

Supported Devices for FPGA Verification and Debug

HDL Coder supports FIL simulation, FPGA data capture, and AXI manager on the devices shown in the following table. The board definition files for these boards are in the Download and Install HDL Coder Support Package for Intel FPGA and SoC Devices. You can add other FPGA boards for use with FIL, FPGA data capture, and AXI manager with FPGA board customization (FPGA Board Customization).

Device FamilyBoardEthernetJTAGPCI ExpressComments
FILFree-Running FILFPGA Data CaptureAXI ManagerFILFPGA Data CaptureAXI ManagerFILFPGA Data CaptureAXI Manager
Intel Agilex 7 Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit✓✓        

Device part number AGIB027R31B1E1V.

This board supports PS Ethernet.

Altera Arria II

 Arria II GX FPGA Development Kit✓  ✓✓✓✓  ✓ 

Altera Arria V

 Arria V SoC Development Board - Rev. C   ✓✓✓✓    
Arria V Starter Kit✓  ✓✓✓✓  ✓ 

Altera Arria 10

 Arria 10 SoC Development Kit✓  ✓✓✓✓   

For Ethernet connection, use Quartus Prime 16.1 or newer.

Arria 10 GX FPGA Development Kit✓  ✓✓✓✓✓ ✓

For Ethernet connection, use Quartus Prime 16.1 or newer.

For FIL over PCI Express, only Quartus Prime Standard edition is supported.

For PCI Express, Quartus Prime 18.0 is not recommended.

Altera Cyclone IV

 Cyclone IV GX FPGA Development Kit✓  ✓✓✓✓  ✓
DE2-115 Development and Education Board✓  ✓✓✓✓   The Altera DE2-115 FPGA development board has two Ethernet ports. FIL uses only Ethernet 0 port. Make sure that you connect your host computer with the Ethernet 0 port on the board via an Ethernet cable.
BeMicro SDK✓  ✓✓✓✓    

Altera Cyclone V

 Cyclone V GX FPGA Development Kit✓  ✓✓✓✓  ✓ 
Cyclone V SoC Development Kit    ✓✓✓✓   Rev. C or D
Cyclone V GT FPGA Development Kit✓  ✓✓✓✓✓ ✓ 
Terasic Atlas-SoC Kit / DE0-Nano SoC Kit   ✓✓✓✓    
Arrow SoCKit Development Kit   ✓✓✓✓    

Altera Cyclone 10 LP

Altera Cyclone 10 LP Evaluation Kit

   ✓✓✓✓    

Altera Cyclone 10 GX

Altera Cyclone 10 GX FPGA Development Kit

   ✓✓✓✓  ✓

Must be used with Quartus Prime Pro.

Altera MAX 10

Arrow DECA MAX 10 FPGA Evaluation Kit

✓  ✓✓✓✓    

Altera Stratix® IV

 Stratix IV GX FPGA Development Kit✓  ✓✓✓✓  ✓ 

Altera Stratix V

DSP Development Kit, Stratix V Edition
✓  ✓✓✓✓✓ ✓

For PCI Express connection, use Quartus Prime Standard 23.1 or earlier.

Limitations

  • For FPGA development boards that have more than one FPGA device, only one such device can be used with FIL.

  • FIL over PCI Express connection is supported only for 64-bit Windows operating systems.

Supported FPGA Device Families for Board Customization

HDL Coder supports the following FPGA device families for board customization; that is, when you create your own board definition file. See FPGA Board Customization.

For board customization, only the JTAG and Ethernet interfaces are supported. The PCI Express interface is not supported. The availability of interfaces varies by board and depends on the specific custom board you select.

You can select and set up an interface for board customization by using the New FPGA Board Wizard tool. For more information about supported interfaces for board customization, see FPGA-in-the-Loop Interface.

  • Arria II GX

  • Arria V

  • Arria 10

  • Cyclone IV GX

  • Cyclone IV E

  • Cyclone V

  • Cyclone 10 LP

  • Cyclone 10 GX

  • MAX 10

  • Stratix IV

  • Stratix V

  • Agilex 7

See Also

Topics