Getting Started with Hardware-Software Co-Design Workflow for Xilinx Zynq UltraScale+ MPSoC Platform

This example shows how to use the HDL Coder™ software to generate a custom HDL IP core which blinks LEDs on the Xilinx® Zynq UltraScale+ MPSoC ZCU102 evaluation kit, and shows how to use Embedded Coder® to generate C code that runs on the ARM® processor to control the LED blink frequency.

Introduction

This example is a step-by-step guide that helps introduce you to the hardware-software co-design workflow for Zynq UltraScale+ MPSoC.

You can use MATLAB® and Simulink® to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. You can then prepare your design for hardware and software implementation on the Xilinx Zynq UltraScale+ MPSoC by deciding which system elements will be performed by the programmable logic, and which system elements will run on the ARM Cortex-A53.

Using the guided workflow shown in this example, you automatically generate HDL code for the programmable logic using HDL Coder, generate C code for the ARM processor using Embedded Coder, and implement the design on the Xilinx Zynq UltraScale+ MPSoC Platform.

In this workflow, you perform the following steps:

  1. Set up your Xilinx Zynq UltraScale+ MPSoC ZCU102 hardware and tools.

  2. Partition your design for hardware and software implementation.

  3. Generate an HDL IP core using HDL Workflow Advisor.

  4. Integrate the IP core into a Xilinx Vivado project and program the Xilinx Zynq UltraScale+ MPSoC hardware.

  5. Generate a software interface model.

  6. Generate C code from the software interface model and run it on the ARM Cortex-A53 processor.

  7. Tune parameters and capture results from the Zynq hardware using External Mode.

Requirements

  1. Xilinx Vivado Design Suite, with supported version listed in the HDL Coder documentation

  2. Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit

  3. HDL Coder Support Package for Xilinx Zynq Platform

  4. Embedded Coder Support Package for Xilinx Zynq Platform

Set up your Xilinx Zynq UltraScale+ MPSoC hardware and tools

1. Set up the Xilinx Zynq UltraScale+ MPSoC ZCU102 evaluation kit as shown in the figure below. To learn more about the ZCU102 hardware setup, please refer to Xilinx documentation.

1.1. Make sure the SW6 switch is set as shown in the figure below, so you can boot up Linux from the SD card.

1.2 Connect your computer to the USB UART connector of ZCU102 using a Micro-USB cable. Make sure your USB device drivers, such as for the Silicon Labs CP210x USB to UART Bridge, are installed correctly. If not, search for the drivers online and install them.

1.3 Connect Xilinx Zynq UltraScale+ MPSoC board to your computer using an Ethernet cable.

2. Install the HDL Coder and Embedded Coder Support Packages for Xilinx Zynq Platform if you haven't already.

2.1 On the MATLAB Home tab in the Environment section, Click Add-Ons > Manage Add-Ons.

2.2 In the Add-On Manager, start the hardware setup process by clicking the setup button for Embedded Coder Support Package for Xilinx Zynq Platform.

3. Make sure you are using the SD card image provided by the Embedded Coder Support Package for Xilinx Zynq Platform.

4. Set up the Zynq hardware connection by entering the following command in the MATLAB command window:

h = zynq

The zynq function logs in to the hardware via COM port and runs the ifconfig command to obtain the IP address of the board. This function also tests the Ethernet connection.

5. You can optionally test the serial connection using the following configuration using a program such as PuTTY™. Baud rate: 115200; Data bits: 8; Stop bits: 1; Parity: None; Flow control: None. You should be able to observe Linux booting log on the serial console when you power cycle the MPSoC board. You must close this serial connection before using the zynq function again.

6. Set up the Xilinx Vivado synthesis tool path using the following command in the MATLAB command window. Use your own Vivado installation path when you run the command.

hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2017.4\bin\vivado.bat');

Partition your design for hardware and software implementation

The first step of the Zynq hardware-software co-design workflow is to decide which parts of your design to implement on the programmable logic, and which parts to run on the ARM processor.

Group all the blocks you want to implement on programmable logic into an Atomic Subsystem. This Atomic Subsystem is the boundary of your hardware-software partition. All the blocks inside this subsystem will be implemented on programmable logic, and all the blocks outside this subsystem will run on the ARM processor.

In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. All the blocks outside of the subsystem led_counter are used for software implementation.

In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. The output port of the hardware subsystem, LED, connects to the LED hardware. The output port, Read_Back, can be used to read data back to the processor.

open_system('hdlcoder_led_blinking');

Generate an HDL IP core using the HDL Workflow Advisor

Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. The generated IP core is designed to be connected to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages all the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Xilinx Vivado environment.

1. Start the IP core generation workflow.

1.1. Open the HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.

1.2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.

1.3. For Target platform, select Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. If you don't have this option, select Get more to open the Support Package Installer. In the Support Package Installer, select Xilinx Zynq Platform and follow the instructions provided by the Support Package Installer to complete the installation.

1.4. Click Run This Task to run the Set Target Device and Synthesis Tool task.

1.5 In the Set Target > Set Target Reference Design task, choose Default system.

1.6. Click Run This Task to run the Set Target Reference Design task.

2. Configure the target interface.

Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4-Lite interface, so HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:7], which connects to the LED hardware on the Zynq board.

2.1 In the Set Target > Set Target Interface task, choose AXI4-Lite for Blink_frequency, Blink_direction, and Read_back.

2.2 Choose LEDs General Purpose [0:7] for LED.

2.3 In the Set Target > Set Target Frequency task, choose Target Frequency as 50 MHz.

3. Generate the IP Core.

To generate the IP core, right-click the Generate RTL Code and IP Core task and select Run to Selected Task.

4. Generate and view the IP core report.

After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated together with the custom IP core. The report describes the behavior and contents of the generated custom IP core.

Integrate the IP core with the Xilinx Vivado environment

In this part of the workflow, you insert your generated IP core into a embedded system reference design, generate an FPGA bitstream, and download the bitstream to the Zynq hardware.

The reference design is a predefined Xilinx Vivado project. It contains all the elements the Xilinx software needs to deploy your design to the Zynq platform, except for the custom IP core and embedded software that you generate.

1. To integrate with the Xilinx Vivado environment, select the Create Project task under Embedded System Integration, and click Run This Task. A Xilinx Vivado project with IP Integrator embedded design is generated, and a link to the project is provided in the dialog window. You can optionally open up the project to take a look.

2. If you have an Embedded Coder license, you can generate a software interface model in the next task, Generate Software Interface Model. The details of the software interface model are explained in the next section of this example, "Generate a software interface model".

3. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure the Run build process externally option is checked, so the Xilinx synthesis tool will run in a separate process from MATLAB. Wait for the synthesis tool process to finish running in the external command window.

4. After the bitstream is generated, select the Program Target Device task. Choose Download for Programming method to download the FPGA bitstream onto the SD card on the Xilinx Zynq UltraScale+ MPSoC board, so your design will be automatically reloaded when you power cycle the Zynq board. click Run This Task to program the Zynq hardware.

After you program the FPGA hardware, the LED starts blinking on your Xilinx Zynq UltraScale+ MPSoC ZCU102 board.

Next, you will generate C code to run on the ARM processor to control the LED blink frequency and direction.

Generate a software interface model

In the HDL Workflow Advisor, after you generate the IP core , You can create a vivado project in step 4.1, you can optionally generate a software interface model in the Embedded System Integration > Generate Software Interface Model task.

The software interface model contains the part of your design that runs in software. It includes all the blocks outside of the HDL subsystem, and replaces the HDL subsystem with AXI driver blocks. If you have an Embedded Coder license, you can automatically generate embedded C code from the software interface model, build it, and run the executable on Linux on the ARM processor. The generated embedded software includes AXI driver code, generated from the AXI driver blocks, that controls the HDL IP core.

Run the Generate Software Interface Model task and see that a new model is generated. The task dialog shows a link to the model.

In the generated software interface model, the "led_counter" subsystem is replaced with the AXI driver blocks which generates the interface logic between the ARM processor and FPGA.

Run the software interface model on Zynq ZCU102 hardware

In this part of the workflow, you configure the generated software interface model, automatically generate embedded C code, and run your model on the ARM processor in the Zynq hardware in External mode.

When you are prototyping and developing an algorithm, it is useful to monitor and tune the algorithm while it runs on hardware. The External mode feature in Simulink enables this capability. In this mode, your algorithm is first deployed to the ARM processor in the Zynq hardware, and then linked with the Simulink model on the host computer through an Ethernet connection.

The main role of the Simulink model is to tune and monitor the algorithm running on the hardware. Because the ARM processor is connected to the HDL IP core through the AXI interface, you can use External mode to tune parameters, and capture data from the FPGA.

  1. In the generated model, open the Configuration Parameters dialog box.

  2. Select Solver and set "Stop Time" to "inf".

  3. From the model menu, select Simulation > Mode > External.

  4. Click the Run button on the model toolstrip. Embedded Coder builds the model, downloads the ARM executable to the Xilinx Zynq UltraScale+ MPSoC ZCU102 hardware, executes it, and connects the model to the executable running on the Zynq hardware.

  5. Double-click the Slider Gain block. Change the Slider Gain value and observe the change in frequency of the LED array blinking on the Zynq hardware. Double-click the Manual Switch block to switch the direction of the blinking LEDs.

  6. Double-click the scope connected to the Read_back output port and observe that the output data of the FPGA IP core is captured and sent back to the Simulink scope.

  7. When you are done changing model parameters, click the Stop button on the model.

Summary

This example shows how the hardware-software co-design workflow helps automate the deployment of your MATLAB and Simulink design to a Xilinx Zynq Ultrascale+ MPSoC. You can explore the best ways to partition and deploy your design by iterating through the workflow.

The following diagram shows the high-level picture of the workflow you went through in this example. To learn more about the hardware and software co-design workflow, please refer to the HDL Coder documentation.