Target Xilinx RFSoC Hardware

HDL Coder™ can generate an IP core, integrate it into your Vivado^® project, and program the Xilinx^® RFSoC hardware.

Generate an HDL IP cores that can integrate into RFSoC devices using Xilinx Vivado Design Suite. Use reference designs for popular RFSoC development kits, so you can generate HDL code and port mappings to I/O and AXI registers to interface with RF tiles and DDR memory, and interactively control the FPGA design from MATLAB.

You can use SoC Blockset™ for system-level modeling of RFSoC devices, configuration of custom RFSoC-based boards, and deployment of complete SoC applications, including executables for ARM^® Cortex^®-A53 processors.