Supported Data Types and Scope

Supported Data Types

HDL Coder™ supports the following subset of MATLAB^® data types.

Types	Supported Data Types	Restrictions
Integer	uint8, uint16, uint32, uint64 int8, int16, int32, int64	In Simulink®, MATLAB Function block ports must use numeric types sfix64 or ufix64 for 64-bit data.
Real	double single	HDL code generated with double or single data types can be used for simulation, but is not synthesizable. When you have floating-point data types, to generate synthesizable HDL code, use: HDL Coder native floating-point when you want to deploy the generated code on any generic ASIC or FPGA. To learn more, see Getting Started with HDL Coder Native Floating-Point Support. FPGA floating-point target libraries when you want to map the Simulink model to an Intel or Xilinx FPGA. To learn more, see Generate HDL Code for Vendor-Specific FPGA Floating-Point Target Libraries.
Character	char
Logical	logical
Fixed point	Scaled (binary point only) fixed-point numbers Custom integers (zero binary point)	Fixed-point numbers with slope (not equal to 1.0) and bias (not equal to 0.0) are not supported. Maximum word size for fixed-point numbers is 65535 bits.
Vectors	unordered {N} row {1, N} column {N, 1}	The maximum number of vector elements allowed is 2^32. Before a variable is subscripted, it must be fully defined.
Matrices	{N, M}	Matrices are supported in the body of the design algorithm and as inputs to the top-level design function. Matrices are not supported with the following HDL workflows: FPGA-in-the-Loop IP Core Generation Cosimulation workflows that use Simulink and SystemVerilog now support vector data types.
Structures	struct	Arrays of structures are not supported. For the IP Core Generation workflow, structures are supported in the body of the design algorithm, but are not supported as inputs to the top-level design function.
Enumerations	enumeration	If your target language is Verilog®, all enumeration member names must be unique within the design. Enumerations at the top-level DUT ports are not supported with the following workflows or verification methods: IP Core Generation workflow FPGA-in-the-Loop Enumerations are supported for Simulink workflows and only for Verilog and SystemVerilog. Enumerations are not supported for VHDL®.

Unsupported Data Types

The following data types are not supported:

• Cell array

• Inf

Scope for Variables

Global variables are not supported for HDL code generation.