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HDL Code Generation from Simulink

Generate HDL code from Simulink® models

Implement your Simulink model or subsystem in hardware by generating HDL code and deploying that code on an Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA). Design the model with blocks that are compatible with HDL code generation. If the model uses floating-point data, use Fixed-Point Designer™ to convert it to a fixed-point model. After you generate HDL code and verify that it matches your original algorithm, deploy the HDL code on your target hardware.


  • Model and Architecture Design
    Supported blocks, best practices, design patterns, compatibility checks, Simscape™ modeling, clocks and reset signals
  • HDL Modeling Guidelines
    Guidelines for designing HDL algorithm in your Simulink model
  • Code Generation
    HDL code generation, code configuration, test bench generation
  • Verification
    Simulation and verification of generated HDL code against original model, and FPGA-in-the-loop
  • Deployment
    Synthesis scripts and deploy generated HDL code to Intel®, Xilinx®, Microchip, Speedgoat®, and custom FPGA boards
  • Speed and Area Optimization
    Improvements through resource sharing, streaming, pipelining, RAM mapping, loop optimization
  • Reports and Scripts
    Traceability, optimization, and resource reports; standards compliance, synthesis scripts