# Implement Sine and Cosine Block with Control Signals

This example shows how to implement the control-signal based SinCos block and use it generate HDL code.

### Open and Run Simulink Model

Specify the input data as a linear sweep through values in the range [-pi, pi]. You can change these values according to your requirements.

```input_values = (-pi:.01/(2*pi):pi)'; ```

Specify the word length for fixed-point datatypes and the latency for the model. The latency depends up on the number of iterations.

```WL_SinCos = 18; latency_SinCos = 12; ```

Open the `hdlcoder_sincos_control` model and specify a stop time sufficient to process all the input combinations. The model has SinCos block that implements the SinCos using CORDIC algorithm. The other trigonometric function blocks, such as Sin, Cos, and Cos + jSin, use the same CORDIC approximation method.

```stoptime_sincos = length(input_values)-1+latency_SinCos; open_system('hdlcoder_sincos_control') sim('hdlcoder_sincos_control') ```

This figure shows the waveform when you simulate the above model. The `dataOut` output is valid when `validOut` is `1`.

### Validate Simulink Output By Using Reference Output

To validate the output of the Simulink model, compare the this output with a reference value. To obtain the reference values, use the `sin` and `cos` function. Compute the reference value for Sine output by using the `sin` function.

```comparison_plot_sincos(sin(input_values),sim_final_sintheta(valid_out),5,'sin'); ```
```Maximum Error sin 1.005291e-03 ```

Compute the reference value for Cosine output by using the `cos` function. The maximum error value is significantly smaller than the output of the model.

```comparison_plot_sincos(cos(input_values),sim_final_costheta(valid_out),6,'cos'); ```
```Maximum Error cos 1.036532e-03 ```

### Generate HDL Code for SinCos Implementation

Check the HDL settings of the model by using the `hdlsaveparams` function.

```hdlsaveparams('hdlcoder_sincos_control') ```
```%% Set Model 'hdlcoder_sincos_control' HDL parameters hdlset_param('hdlcoder_sincos_control', 'HDLSubsystem', 'hdlcoder_sincos_control/SinCos'); hdlset_param('hdlcoder_sincos_control', 'ResetType', 'Synchronous'); hdlset_param('hdlcoder_sincos_control', 'SynthesisTool', 'Xilinx Vivado'); hdlset_param('hdlcoder_sincos_control', 'SynthesisToolChipFamily', 'Virtex7'); hdlset_param('hdlcoder_sincos_control', 'SynthesisToolDeviceName', 'xc7v2000t'); hdlset_param('hdlcoder_sincos_control', 'SynthesisToolPackageName', 'fhg1761'); hdlset_param('hdlcoder_sincos_control', 'SynthesisToolSpeedValue', '-2'); hdlset_param('hdlcoder_sincos_control', 'TargetDirectory', 'hdl_prj\hdlsrc'); hdlset_param('hdlcoder_sincos_control', 'TargetFrequency', 500); hdlset_param('hdlcoder_sincos_control/SinCos/LumpLatency', 'Architecture', 'MATLAB Datapath'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_sincos_control/SinCos/LumpLatency', 'FlattenHierarchy', 'on'); hdlset_param('hdlcoder_sincos_control/SinCos/LumpLatency1', 'Architecture', 'MATLAB Datapath'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_sincos_control/SinCos/LumpLatency1', 'FlattenHierarchy', 'on'); hdlset_param('hdlcoder_sincos_control/SinCos/SinCos', 'Architecture', 'Cordic'); hdlset_param('hdlcoder_sincos_control/SinCos/ValidLine', 'Architecture', 'MATLAB Datapath'); % Set SubSystem HDL parameters hdlset_param('hdlcoder_sincos_control/SinCos/ValidLine', 'FlattenHierarchy', 'on'); ```

To generate HDL code for the SinCos block in the model, use the `makehdl` function.

```makehdl('hdlcoder_sincos_control/SinCos') close_system('hdlcoder_sincos_control') close all; ```
```### Generating HDL for 'hdlcoder_sincos_control/SinCos'. ### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_sincos_control', { 'HDL Code Generation' } )">hdlcoder_sincos_control</a> for HDL code generation parameters. ### Running HDL checks on the model 'hdlcoder_sincos_control'. ### Begin compilation of the model 'hdlcoder_sincos_control'... ### Begin compilation of the model 'hdlcoder_sincos_control'... ### Working on the model 'hdlcoder_sincos_control'... ### <a href="matlab:configset.internal.open('hdlcoder_sincos_control','AdaptivePipelining')">'AdaptivePipelining'</a> is set to 'Off' for the model. 'AdaptivePipelining' can improve the achievable clock frequency and reduce the area usage on FPGA boards. To enable adaptive pipelining, please set the option to 'On'. When adaptive pipelining is enabled, it inserts pipeline registers to create patterns that efficiently map blocks to DSP units on the target FPGA device. ### <a href="matlab:configset.internal.open('hdlcoder_sincos_control','LUTMapToRAM')">'LUTMapToRAM'</a> is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware. To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'. ### Working on... <a href="matlab:configset.internal.open('hdlcoder_sincos_control', 'GenerateModel')">GenerateModel</a> ### Begin model generation 'gm_hdlcoder_sincos_control' .... ### Rendering DUT with optimization related changes (IO, Area, Pipelining)... ### Model generation complete. ### Begin VHDL Code Generation for 'hdlcoder_sincos_control'. ### Working on hdlcoder_sincos_control/SinCos/SinCos_cordic_nw as hdl_prj/hdlsrc/hdlcoder_sincos_control/SinCos_cordic_nw.vhd. ### Working on hdlcoder_sincos_control/SinCos as hdl_prj/hdlsrc/hdlcoder_sincos_control/SinCos.vhd. ### Code Generation for 'hdlcoder_sincos_control' completed. ### Creating HDL Code Generation Check Report file:///tmp/Bdoc23b_2361005_1061343/tpe92f0394/hdlcoder-ex40921781/hdl_prj/hdlsrc/hdlcoder_sincos_control/SinCos_report.html ### HDL check for 'hdlcoder_sincos_control' complete with 0 errors, 1 warnings, and 2 messages. ### HDL code generation complete. ```

### SinCos Block Synthesis Performance

This figure shows the SinCos block synthesis performance on the Xilinx Virtex 7 and Intel Stratix V devices.