Integrate HDL IP Core with Microchip PolarFire SoC Icicle Kit Reference Design
This example shows how to use the hardware-software co-design workflow to blink LEDs at various frequencies on the Microchip PolarFire SoC Icicle kit.
This example is a step-by-step guide that helps you use HDL Coder™ to generate a custom HDL IP core that blinks LEDs on the Microchip PolarFire SoC Icicle kit.
You can use MATLAB® and Simulink® to design, simulate, and verify your application, perform what-if scenarios with algorithms, and optimize parameters. You can then prepare your design for hardware and software implementation on the PolarFire SoC Icicle Kit by deciding which system elements are performed by the programmable logic, and which system elements are run on the ARM Cortex-A9.
Using the guided workflow shown in this example, you automatically generate HDL code for the programmable logic by using HDL Coder and implement the design on the Microchip PolarFire SoC Icicle Kit.
In this workflow, you perform these tasks:
Set up your PolarFire SoC hardware and tools.
Partition your design for hardware and software implementation.
Generate an HDL IP core by using HDL Workflow Advisor.
Integrate the IP core into a Microchip Libero project and program the PolarFireSoC hardware.
Microchip Libero Design Suite, with supported version listed in the HDL Language Support and Supported Third-Party Tools and Hardware.
Microchip PolarFire SoC Icicle Kit
HDL Coder Support Package for Microchip FPGA and SoC Devices
Set Up PolarFire SoC Hardware and Tools
1. Set up the Microchip PolarFire SoC Icicle Kit as shown in the figure. To learn more about the PolarFire SoC hardware setup, see PolarFire SoC Icicle Kit Quickstart Card.
Connect your computer to the USB UART connector by using a Micro-USB cable. Make sure that your USB device drivers, such as for the Silicon Labs CP210x USB to UART Bridge, are installed correctly. If not, search for the drivers online and install them.
2. Connect your computer and the PolarFire SoC board using an Ethernet cable.
3. Install the HDL Coder Support Packages for Microchip FPGA and SoC Devices if you have not already done so. To start the installer, on the MATLAB toolstrip, click Add-Ons > Get Hardware Support Packages. Search for HDL Coder Support Packages for Microchip FPGA and SoC Devices and install them.
4. Make sure that you are using the SD card image provided by Microchip from Github Link.
5. Set up the PolarFire SoC hardware connection in this MATLAB Command Window.
6. You can optionally test the serial connection by using the configuration that uses a program such as PuTTY™. Baud rate:
115200; Data bits:
8; Stop bits:
None; Flow control:
None. You can see Linux booting log on the serial console when you Power Cycle the PolarFire SoC board.
7. Set up the Microchip Libero SoC synthesis tool path in the MATLAB Command Window. When you run the command, use own Microchip Libero installation path.
hdlsetuptoolpath('ToolName', 'Microchip Libero SoC', 'ToolPath', 'C:\Microsemi\Libero_SoC_v12.6\Designer\bin\libero.exe');
Partition your Design for Hardware and Software Implementation
For the PolarFire SoC hardware-software co-design workflow, decide which parts of your design to implement on the programmable logic and which parts to run on the ARM processor.
Group all the blocks that you want to implement on programmable logic into an atomic subsystem. This atomic subsystem is the boundary of your hardware-software partition. The blocks inside this subsystem are implemented on programmable logic and the blocks outside this subsystem run on the ARM processor.
In this example, the subsystem led_counter is the hardware subsystem. It models a counter that blinks the LEDs on an FPGA board. Two input ports, Blink_frequency and Blink_direction, are control ports that determine the LED blink frequency and direction. The blocks outside of the subsystem led_counter are for software implementation.
In Simulink, you can use the Slider Gain or Manual Switch block to adjust the input values of the hardware subsystem. In the embedded software, this means the ARM processor controls the generated IP core by writing to the AXI interface accessible registers. The output port of the hardware subsystem, LED, connects to the LED hardware. You can use the output port, Read_Back, to read data back to the processor.
Generate HDL IP Core by using the HDL Workflow Advisor
You can generate a sharable and reusable IP core module from a Simulink model. The generated IP core connects to an embedded processor on an FPGA device. HDL Coder generates HDL code from the Simulink blocks and generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. HDL Coder packages the generated files into an IP core folder. You can then integrate the generated IP core with a larger FPGA embedded design in the Microchip Libero environment.
Start IP Core Generation Workflow.
1. Open the HDL Workflow Advisor from the
hdlcoder_led_blinking/led_counter subsystem by right-clicking the
led_counter subsystem, and choosing HDL Code > HDL Workflow Advisor.
2. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation.
3. For Target platform, select Microchip PolarFire SoC Icicle kit. If you don't have this option, select Get more to open the Support Package Installer.
4. Click Run This Task to run the Set Target Device and Synthesis Tool task.
5. In the Set Target > Set Target Reference Design task, Reference Design Default system is selected by default.
6. Click Run This Task to run the Set Target Reference Design task.
Configure Target Interface.
Map each port in your DUT to one of the IP core target interfaces. In this example, input ports Blink_frequency and Blink_direction are mapped to the AXI4 interface. HDL Coder generates AXI interface accessible registers for them. The LED output port is mapped to an external interface, LEDs General Purpose [0:3], which connects to the LED hardware on the PolarFire SoC board.
1. In the Set Target > Set Target Interface task, choose AXI4 for Blink_frequency, Blink_direction, and Read_back.
2. Choose LEDs General Purpose [0:3] for LED.
3. In the Set Target > Set Target Frequency task, choose Target Frequency as 50 MHz.
Generate IP Core
1. Right-click the Generate RTL Code and IP Core task and select Run to Selected Task.
2. Generate and view the IP core report.
After you generate the custom IP core, the IP core files are in the ipcore folder within your project folder. An HTML custom IP core report is generated with the custom IP core. The report describes the behavior and contents of the generated custom IP core.
3. Register Address Mapping.
IP Core Generation Report also contains the details about Target Platform Interface of your model. The figure shows the AXI4 interface mapped to the hdlcoder_led_blinking_4bit model ports. The table in IP Core Generation Report shows the interface mapping address of each AXI4 slave register. These addresses are used to read the AXI4 slave input registers.
Integrate IP Core with Microchip Libero SoC Environment
Insert your generated IP core into a embedded system reference design, generate an FPGA bitstream, and download the bitstream to the PolarFire SoC hardware.
The reference design is a predefined Microchip Libero project. It contains the elements the Libero software requires to deploy your design to the PolarFire SoC board, except for the custom IP core.
1. To integrate with the Microchip Libero environment, select the Create Project task under Embedded System Integration. Click Run This Task. A Microchip Libero project with the IP Integrator embedded design is generated.
A link to the project is provided in the dialog box. You can optionally open up the project to take a look. From the block diagram in Libero tool, you can see the HDL Coder generated IP core led_count_ip_0 is connected to the Microprocessor Subsystem through the AXI interface.
2. Build the FPGA bitstream in the Build FPGA Bitstream task. Make sure that you select Run build process externally option so that Libero synthesis tool will runs in a separate process from MATLAB. Wait until workflow_task_runExtShell.log file gets generated in libero_ip_prj folder.
3. After the bitstream is generated, select the Program Target Device task. JTAG option for Programming method will be selected automatically to download the FPGA bitstream onto the PolarFire SoC board. Your design will be automatically reloaded when you power cycle the PolarFire SoC board. click Run This Task to program the PolarFire SoC hardware.
After you program the FPGA hardware, the LED starts blinking on your PolarFire SoC board.
Read Values of the AXI4 Slave input registers
The AXI4 slave base address is used together with interface mapping address (from IP Core Generation report) to read the value of AXI4 slave input registers. These address mapping details are used to read the AXI4 slave registers. You can perform the readback of input registers in these ways:
Using the Devmem command
Using the MATLAB FPGA Prototyping API Script
Readback of AXI4 Slave Input Registers Using Devmem Command
Devmem command can be used in Putty or Hyper Terminal. Once the bitstream is programmed into the target device, open Putty or hyper terminal using serial interface. From Register Address Mapping , AXI4 Slave Base Address is 0x60000000. You can perform read and write operation on AXI4 Slave registers using Base Address and Address Offset. To use devmem command for writing and reading value of Blink_frequency_Data register, use these steps.
1. Read the data from address '60000100':
You get the value as 0x00000000.
2. Write some value in address '60000100':
devmem2 0x60000100 w 0x1
3. Reread the address '60000100':
You get the value as 0x00000001.
This example shows how the hardware and software co-design workflow helps automate the deployment of your MATLAB and Simulink design to a Microchip PolarFire SoC Icicle Kit. You can explore the best ways to partition and deploy your design by iterating through the workflow.
The following diagram shows high-level picture of the workflow you went through in this example. To learn more about the hardware and software co-design workflow, see Hardware-Software Co-Design Workflow for SoC Platforms.