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Structure of Generated Script Files

A generated EDA script consists of an initialization phase, command-per-file phase, and a termination phase.

The sections are generated and executed in the following order:

  1. An initialization (Init) phase. The Init phase performs the required setup actions, such as creating a design library or a project file. Some arguments to the Init phase are implicit, for example, the top-level entity or module name.

  2. A command-per-file phase (Cmd). This phase of the script is called iteratively, once per generated HDL file or once per signal. On each call, a different file or signal name is passed in.

  3. A termination phase (Term). This is the final execution phase of the script. One application of this phase is to execute a simulation of HDL code that was compiled in the Cmd phase. The Term phase does not take arguments.

The HDL Coder™ software generates scripts by passing format strings to the fprintf function. Using the GUI options (or makehdl and makehdltb properties) summarized in the following sections, you can pass in customized format names to the script generator. Some of these format names take arguments, such as the top-level entity or module name, or the names of the VHDL®, Verilog® or SystemVerilog files in the design.

You can use valid fprintf formatting characters. For example, '\n' inserts a newline into the script file.