The Triggered Subsystem block is a Subsystem block that executes each time the control signal has a trigger value. To learn more about the block, see Triggered Subsystem.
When using triggered subsystems in models targeted for HDL code generation, consider the following:
For synthesis results to match Simulink® results, drive the trigger port with registered logic (with a synchronous clock) on the FPGA.
It is good practice to put unit delays on Triggered Subsystem output signals. Doing so prevents the code generator from inserting extra bypass registers in the HDL code.
The use of triggered subsystems can affect synthesis results in the following ways:
In some cases, the system clock speed can drop by a small percentage.
Generated code uses more resources, scaling with the number of triggered subsystem instances and the number of output ports per subsystem.
When you connect outputs from a Signal Builder block to a triggered subsystem, you might need to use a Rate Transition block. To run all triggered subsystem ports at the same rate:
If the trigger source is a Signal Builder block, but the other triggered subsystem inputs come from other sources, insert a Rate Transition block into the signal path before the trigger input.
If all inputs (including the trigger) come from a Signal Builder block, they have the same rate, so special action is not required.
Using the trigger as clock in triggered subsystems enables you to partition your design into different clock regions in the generated code. Make sure that the Clock edge setting in the Configuration Parameters dialog box matches the Trigger type of the Trigger block inside the triggered subsystem.
For example, you can model:
A design with clocks that run at the same rate, but out of phase.
Clock regions driven by an external or internal clock divider.
Clock regions driven by clocks whose rates are not integer multiples of each other.
Internally generated clocks.
Clock gating for low-power design.
Using the trigger as clock for triggered subsystems can result in timing mismatches of one cycle during testbench simulation.
When you use the trigger as clock in triggered subsystems, each triggered subsystem input or output data signal must have delays immediately outside and immediately inside the subsystem. These delays act as a synchronization interface between the regions running at different rates.
In HDL Code Generation > Global Settings > Ports tab, select Use trigger signal as clock.
TriggerAsClock property using
example, to generate HDL code that uses the trigger signal as clock for
triggered subsystems in a DUT subsystem,
myDUT, in a
HDL Coder™ supports HDL code generation for triggered subsystems that meet the following conditions:
The triggered subsystem is not the DUT.
The subsystem is not both triggered and enabled.
The trigger signal is a scalar.
Outputs of the triggered subsystem have an initial value of 0.
All inputs and outputs of the triggered subsystem (including the trigger signal) run at the same rate.
The Show output port parameter of the Trigger block
is set to
The Latch input by delaying outside signal check box is not selected on the Inport block inside the Triggered Subsystem.
If the DUT contains the following blocks,
RAMArchitecture is set to
Dual Port RAM
Simple Dual Port RAM
Single Port RAM
The triggered subsystem does not contain the following blocks:
HDL Cosimulation blocks for HDL Verifier™
Pixel Stream FIFO (Vision HDL Toolbox™)
PN Sequence Generator, if the Use trigger signal as clock option is selected.