HDL Constructs

Representing VHDL Constants with Aggregates

By default, the coder represents constants as scalars or aggregates depending on the size and type of the data. The coder represents values that are less than 2³² – 1 as integers and values greater than or equal to 2³² – 1 as aggregates. These VHDL^® constant declarations are examples of declarations generated by default for values less than 32 bits:

CONSTANT coeff1: signed(15 DOWNTO 0) := to_signed(-60, 16); -- sfix16_En16
CONSTANT coeff2: signed(15 DOWNTO 0) := to_signed(-178, 16); -- sfix16_En16

If you prefer that constant values be represented as aggregates, set the Represent constant values by aggregates as follows:

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab.
Select Represent constant values by aggregates, as shown this figure.

The preceding constant declarations would now appear as follows:

CONSTANT coeff1: signed(15 DOWNTO 0) := (5 DOWNTO 3 => '0',1 DOWNTO 0 => '0,OTHERS =>'1');
CONSTANT coeff2: signed(15 DOWNTO 0) := (7 => '0',5 DOWNTO 4 => '0',0 => '0',OTHERS =>'1');

Command-Line Alternative: Use the generatehdl function with the property UseAggregatesForConst to represent constants in the HDL code as aggregates.

Unrolling and Removing VHDL Loops

By default, the coder supports VHDL loops. However, some EDA tools do not support them. If you are using such a tool along with VHDL, you can unroll and remove FOR and GENERATE loops from the generated VHDL code. Verilog^® code is already unrolled.

To unroll and remove FOR and GENERATE loops,

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Select Loop unrolling, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property LoopUnrolling to unroll and remove loops from generated VHDL code.

Using the VHDL rising_edge Function

The coder can generate two styles of VHDL code for checking for rising edges when the filter operates on registers. By default, the generated code checks for a clock event, as shown in the ELSIF statement of this VHDL process block.

Delay_Pipeline_Process : PROCESS (clk, reset)
BEGIN
  IF reset = '1' THEN
    delay_pipeline(0 TO 50) <= (OTHERS => (OTHERS => '0'));
  ELSEIF clk'event AND clk = '1' THEN
    IF clk_enable = '1' THEN
      delay_pipeline(0) <= signed(filter_in);
      delay_pipeline(1 TO 50) <= delay_pipeline(0 TO 49);
    END IF;
  END IF;
END PROCESS Delay_Pipeline_Process ;

If you prefer, the coder can produce VHDL code that applies the VHDL rising_edge function instead. For example, the ELSIF statement in the preceding process block would be replaced with this statement:

  ELSIF rising_edge(clk) THEN

To use the rising_edge function,

Click Global Settings in the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Select Use 'rising_edge' for registers, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property UseRisingEdge to use the VHDL rising_edge function to check for rising edges during register operations.

Suppressing the Generation of VHDL Inline Configurations

VHDL configurations can be either inline with the rest of the VHDL code for an entity or external in separate VHDL source files. By default, the coder includes configurations for a filter within the generated VHDL code. If you are creating your own VHDL configuration files, suppress the generation of inline configurations.

To suppress the generation of inline configurations,

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Clear Inline VHDL configuration, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property InlineConfigurations to suppress the generation of inline configurations.

Specifying VHDL Syntax for Concatenated Zeros

In VHDL, the concatenation of zeros can be represented in two syntax forms. One form, '0' & '0', is type-safe. This syntax is the default. The alternative syntax, "000000...", can be easier to read and is more compact, but can lead to ambiguous types.

To use the syntax "000000..." for concatenated zeros,

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Clear Concatenate type safe zeros, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property SafeZeroConcat to use the syntax "000000...", for concatenated zeros.

Specifying Input Type Treatment for Addition and Subtraction Operations

By default, generated HDL code operates on input data using data types as specified by the filter design, and then converts the result to the specified result type.

Typical DSP processors type cast input data to the result type before operating on the data. Depending on the operation, the results can be different. If you want generated HDL code to handle result typing in this way, use the Cast before sum option as follows:

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Select Cast before sum, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property CastBeforeSum to cast input values to the result type for addition and subtraction operations.

Relationship With Cast Before Sum in Filter Designer

The Cast before sum option is related to the Filter Designer setting for the quantization option Cast signals before sum as follows:

Some filter object types do not have the Cast signals before sum property. For such filter objects, Cast before sum is effectively off when HDL code is generated; it is not relevant to the filter.
Where the filter object does have the Cast signals before sum property, the coder by default follows the setting of Cast signals before sum in the filter object. This setting is visible in the UI. If you change the setting of Cast signals before sum, the coder updates the setting of Cast before sum.
However, by explicitly setting Cast before sum, you can override the Cast signals before sum setting passed in from Filter Designer.

Suppressing Verilog Time Scale Directives

In Verilog, the coder generates time scale directives (ˋtimescale) by default. This compiler directive provides a way of specifying different delay values for multiple modules in a Verilog file.

To suppress the use of ˋtimescale directives,

Select the Global Settings tab on the Generate HDL tool.
Select the Advanced tab. The Advanced pane appears.
Clear Use Verilog ˋtimescale directives, as shown in this figure.

Command-Line Alternative: Use the generatehdl function with the property UseVerilogTimescale to suppress the use of time scale directives.

Using Complex Data and Coefficients

The coder supports complex coefficients and complex input signals.

Enabling Code Generation for Complex Data

To generate ports and signal paths for the real and imaginary components of a complex input signal, set Input complexity to Complex. The default setting for Input complexity is Real, disabling generation of ports for complex input data.

The corresponding command-line property is InputComplex. By default, InputComplex is set to 'off', disabling generation of ports for complex input data. To enable generation of ports for complex input data, set InputComplex to 'on', as in this code example:

filt = design(fdesign.lowpass,'equiripple','Filterstructure','dffir','SystemObject',true);
generatehdl(filt,numerictype(1,16,15),'InputComplex','on')

This VHDL code excerpt shows the entity definition generated by the preceding commands:

ENTITY firfilt IS
   PORT( clk                :   IN    std_logic; 
         clk_enable         :   IN    std_logic; 
         reset              :   IN    std_logic; 
         filter_in_re       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_in_im       :   IN    std_logic_vector(15 DOWNTO 0); -- sfix16_En15
         filter_out_re      :   OUT   std_logic_vector(37 DOWNTO 0); -- sfix38_En31
         filter_out_im      :   OUT   std_logic_vector(37 DOWNTO 0)  -- sfix38_En31
         );

END firfilt;

In the code excerpt, the port names generated for the real components of complex signals have the default postfix '_re', and port names generated for the imaginary components of complex signals have the default postfix '_im'.

Setting the Port Name Postfix for Complex Ports

Two code generation properties let you customize naming conventions for the real and imaginary components of complex signals in generated HDL code. These properties are:

The Complex real part postfix option (corresponding to the ComplexRealPostfix command-line property) specifies a character vector to be appended to the names generated for the real part of complex signals. The default postfix is '_re'.
The Complex imaginary part postfix option (corresponding to the ComplexImagPostfix command-line property) specifies a character vector to be appended to the names generated for the imaginary part of complex signals. The default postfix is '_im'.