Filter Design HDL Coder
Filter Design HDL Coder™ generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.
The Filter Design HDL Coder product will be discontinued in a future release. Instead, you can model hardware behavior, and generate HDL code by using System objects or Simulink® blocks from DSP HDL Toolbox™. These objects and blocks include hardware-friendly control signals and architecture options. To generate HDL code from DSP HDL Toolbox objects and blocks, you must also have the HDL Coder™ product.
Generate HDL code for fixed-point filters
HDL code generation startup, language selection, HDL code generation scripts
Single rate, multirate, cascaded, other advanced digital filters
Resource usage, clock speed, chip area, latency
File names and locations, identifiers and comments, ports and resets, HDL language constructs
HDL test bench generation, and cosimulation with third party EDA tools
Compilation, simulation, and synthesis script generation